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Asics Jobs in Austin

11 open positions · Updated 1 month ago

Showing 11 of 11 positions

Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enabling global connectivity.

SpaceX Austin, TX Published 1 month ago

C++ automated test equipment ASICs Siemens Tessent DFT

Flexible on stack

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Sr. IC Package Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. IC Package Design Engineer to develop cutting-edge ASICs for space and ground infrastructures.

SpaceX Austin, TX Published 1 month ago

SIWave BGA ADS HFSS RFIC

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 1 month ago

C++ Verilog Siemens Tessent ATE RTL

Flexible on stack

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Austin, TX Published 1 month ago

FinFET Scripting ASIC EDA tools physical design

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Sr. Technical Project Lead (Silicon Engineering) Visa

Lead complex silicon projects at SpaceX, driving the development of next-generation ASICs for Starlink's global connectivity.

SpaceX Austin, TX Published 1 week ago

Project Management Digital ASIC Design Silicon Engineering PCB FPGA

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Austin, TX Published 2 months ago

FinFET EDA RTL Makefile ASIC

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 3 months ago

Verilog AHB ASIC Python System Verilog

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Sr. Full Chip Physical Verification Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 2 months ago

IC Validator Calibre Makefile ASIC Python

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