Join Ambiq as an intern to support the development of standard cell and memory compiler IP for edge AI SoCs.
Posted by employer 2 days ago
First seen on Joblaze 1 day ago
Last verified on the company career page 1 day ago
Not disclosed in this posting: compensation, years of experience, work arrangement, visa sponsorship.
Joblaze summary
The AI-Assisted Foundation IP Development Intern at Ambiq focuses on supporting the design and characterization of standard cell and memory compiler IP for edge AI systems. Key responsibilities include running simulations, analyzing data trends using Python, and assisting with layout tasks to ensure efficient circuit design. This role is ideal for rising juniors or seniors pursuing degrees in electrical engineering or related fields, particularly those with a background in digital logic and machine learning. Ambiq's collaborative environment encourages interns to tackle complex challenges in energy-efficient technology.
Quick facts
- What's the tech stack?
- Joblaze extracted these technologies from the posting: AI/ML, Liberate, Monte Carlo, Python, VLSI, pandas.
- What seniority level is this role?
- Ambiq targets intern candidates for this position.
- Is this full-time or contract?
- Internship for this AI-Assisted Foundation IP Development Intern role at Ambiq.
From the original posting
AI-Assisted Foundation IP Development Intern
About the Role
Part of Foundation IP team on standard cell and memory compiler IP for edge AI SoCs — including using data analysis and ML to spot trends in characterization data and flag outliers early.
Responsibilities
- Support circuit design, spice/Monte Carlo simulation and layout of standard cells
- Perform layout tasks (placement, routing, DRC/LVS cleanup) for foundation IP
- Characterize standard cells (timing, power, noise) across PVT corners
- Run characterization flows using tools like Liberate
- Analyze characterization data using Python (pandas, scikit-learn) to find trends and outliers
- Build simple predictive models to flag likely failures and reduce simulation runs
- Help debug mismatches between simulated and characterized results
- Document findings and share with the IP team
Qualifications
- Pursuing a BS in EE, CE, Microelectronics, or related field (rising Junior/Senior)
- Coursework in digital logic, Analog, AI/ML, data Science, VLSI, or semiconductor devices
- Basic understanding of circuit design and IC layout (DRC/LVS) concepts
- Working knowledge of Python and basic ML concepts (regression, clustering)
- Comfort working with large datasets
Nice to Have
- Exposure to layout/schematic tools (Virtuoso, Calibre) or characterization tools (Liberate, Tempus)
- A class project applying ML to engineering or scientific data
- Interest in low-power IP for edge AI/IoT
Standard company text repeated across Ambiq's postings is omitted here.