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Senior Mask Layout Engineer

Join IonQ as a Senior Mask Layout Engineer to lead the development of cutting-edge quantum computing technologies.

Location
College Park, Maryland, United States
Compensation
$126.9k–$166.1k/yr
Level
senior
Type
full time · Hybrid

Posted by employer 1 day ago

First seen on Joblaze 11 hours ago

Last verified on the company career page 11 hours ago

Apply at IonQ → Save job Scanned from ionq.com

What you'll build

  • Conduct Python-based layout for full-reticle tapeouts
  • Develop and maintain internal component PCell libraries
  • Interface with designers and engineers to define layout rules
  • Implement physical verification checks of layouts
  • Develop detailed documentation of tapeouts

Must have

  • Bachelor’s degree in Photonics, Physics, Electrical Engineering, or related field
  • 2+ years of experience with Python-based mask layout software packages

Nice to have

  • M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field
  • 5+ years experience in generating layout files for complex semiconductor flows
  • Experience with commercial simulation, verification, and layout environments

Practical constraints

  • Travel: Up to 10%

Requirements

Experience
2–5 years
Education
Bachelor's degree

Not disclosed in this posting: visa sponsorship.

Benefits

401k Match Unlimited PTO Equity/Stock Options Health Insurance Parental Leave

Joblaze summary

The Senior Mask Layout Engineer at IonQ is responsible for managing full-reticle tapeouts for trapped-ion quantum computers, which involves both photonic and analog electronic layers. This role requires expertise in Python-based layout software and a solid understanding of semiconductor manufacturing processes, along with experience in generating complex layout files. Ideal candidates will have a background in photonics or electrical engineering, with several years of relevant experience, particularly in semiconductor flows. IonQ's collaborative environment emphasizes cross-functional teamwork to advance quantum technology.

Joblaze insights

  • Listed today — first seen on Joblaze September 25, 2026. Last confirmed on IonQ's careers page September 25, 2026.
  • This exact title is also open at 1 other location at IonQ: College Park, Maryland, United States.
  • Salary band is in line with the typical range for comparable tech roles (median ~$126,887).
  • Starts above 15% of 238 comparable senior other roles in United States that list Python we track (median $150,000 across 53 companies). See Python salary trends
  • Python appears in 16.5% of 2255 comparable senior other roles in United States; Semiconductor appears in 0.3% of 2255 comparable senior other roles in United States.

Quick facts

Is the Senior Mask Layout Engineer role remote?
It's hybrid — IonQ expects some on-site time in College Park, Maryland, United States.
What's the salary range?
IonQ lists $126,887–$166,127 for this role.
How much experience is required?
2–5 years of relevant experience for this Senior Mask Layout Engineer role.
Where is the role based?
IonQ is hiring for this position in College Park, Maryland, United States.
What's the tech stack?
Joblaze extracted these technologies from the posting: Analog Electronics, Python, Semiconductor, mask layout, photonic.
What seniority level is this role?
IonQ targets senior candidates for this position.
Is this full-time or contract?
Full-time for this Senior Mask Layout Engineer role at IonQ.

From the original posting

About IonQ:

We are looking for a Senior Mask Layout Engineer on the Fab Tapeout and Validation Team. As a Senior Mask Layout Engineer, you’ll be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world’s best quantum computers to solve the world’s most complex problems.

In this role, you will be the owner of full-reticle tapeouts for use in trapped-ion quantum computers, which could include both photonic and analog electronic layers. In addition, you will help develop and maintain the internal PDK and circuit layout libraries, as well as write scripts to automate the layout of masks for tapeouts. You will also have the opportunity to work closely with the photonic and ion trap design and testing teams to help develop new and game-changing quantum technology to enable scalable quantum computing, memory, and networking.

Responsibilities:

  • Conduct Python-based layout for full-reticle tapeouts with commercial foundries
  • Develop and maintain internal component PCell and automated circuit layout libraries
  • Interface with designers, test engineers, packaging engineers, and foundry team to define layout rules and component designs
  • Implement physical verification checks of layouts, including DRC and LVS
  • Develop detailed documentation of tapeouts and lead layout reviews with other team members
  • Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows

You’d be a good fit with:

  • Bachelor’s degree in Photonics, Physics, Electrical Engineering, or related field, or equivalent practical experience
  • Knowledge of semiconductor manufacturing processes and techniques
  • Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation
  • 2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout

You’d be a great fit with:

  • M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field
  • 5+ years experience in generating layout files for complex semiconductor flows with custom elements, such as MEMS, integrated photonics, or superconducting circuits
  • Past ownership of full-reticle tapeouts with commercial foundries
  • Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys
  • Familiarity with photonic and/or analog electronic device principles including design, test, and fabrication
  • Proficiency in physical verification including DRC, LVS, and ERC
  • Experience with semiconductor and/or photonic workflows for tapeout with commercial foundries
  • Excellent verbal and written communication skills
  • A meticulous attention to detail and excellent track record of documenting requirements, implementation plan, and tracking progress
  • Ability to work independently, prioritizing tasks and managing time effectively in a deadline-oriented environment


Location:
This role is hybrid/onsite in College Park, MD location.
Travel: Up to 10%
Job ID: 1303

The approximate base salary range for this position is $126,887 - $166,127. The total compensation package includes base, bonus, and equity.

Compensation will vary based on individual factors such as education, qualifications, and experience of the final candidate(s), specific office location, and calibration against relevant market data and internal team equity. Posted base salary figures are subject to change as new market data becomes available. Our benefits include comprehensive medical, dental, and vision plans, matching 401(k), unlimited PTO and paid holidays, parental/adoption leave, legal insurance, and a home technology stipend. Details of participation in these benefit plans will be provided when a candidate receives an offer of employment.

Standard company text repeated across IonQ's postings is omitted here.

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