Posted by employer 3 days ago
First seen on Joblaze 17 hours ago
Last verified on the company career page 17 hours ago
Not disclosed in this posting: compensation, years of experience, visa sponsorship.
Joblaze summary
In this role, the engineer is responsible for the physical layout and full-chip integration of system-on-chip (SoC) designs, ensuring that all components function seamlessly together. Proficiency in layout tools and a strong understanding of semiconductor design principles are essential for success. This position is suited for experienced professionals with a background in integrated circuit design and physical design methodologies. Intel's focus on innovation and technology advancement provides a collaborative environment for engineers to contribute to complex projects.
Joblaze insights
- Listed today — first seen on Joblaze September 19, 2026. Last confirmed on Intel's careers page September 19, 2026.
Quick facts
- Is the Senior SoC Physical Layout & Full-Chip Integration Engineer role remote?
- No — this is an on-site role in Hillsboro, Oregon, United States.
- Where is the role based?
- Intel is hiring for this position in Hillsboro, Oregon, United States.
- What seniority level is this role?
- Intel targets senior candidates for this position.
- Is this full-time or contract?
- Full-time for this Senior SoC Physical Layout & Full-Chip Integration Engineer role at Intel.