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Senior Chip Level Packaging Jobs

35 open positions · Updated 2 months ago

Average salary: 155.5k–217.1k/yr

Showing 20 of 35 positions

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SpaceX

Join SpaceX as a Sr. Full Chip Physical Verification Engineer to develop cutting-edge silicon for the Starlink network.

SpaceX Irvine, CA $160k–$225k/yr Published 1 month ago
Flexible on stack
SpaceX

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Sunnyvale, CA $170k–$230k/yr Published 1 month ago
Flexible on stack
SpaceX

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Irvine, CA $160k–$220k/yr Published 1 month ago
Flexible on stack
SpaceX

Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Irvine, CA $125k–$175k/yr Published 1 month ago
Flexible on stack
SpaceX

Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Sunnyvale, CA $135k–$185k/yr Published 1 month ago
Flexible on stack
SpaceX

Join SpaceX as a Sr. RF Front-End Module Design Engineer to develop advanced RF modules for the Starlink Mobile network.

SpaceX Sunnyvale, CA $170k–$235k/yr Published 1 month ago
Flexible on stack
SpaceX

Join SpaceX as a Sr. RF Front-End Module Design Engineer to develop cutting-edge RF modules for the Starlink Mobile network.

SpaceX Irvine, CA $160k–$225k/yr Published 1 month ago
Flexible on stack
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