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Systemverilog Jobs in Sunnyvale

2 open positions · Updated 1 month ago

Average salary: 127.5k–210k/yr

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Design Verification Engineer Remote

Cerebras Systems Sunnyvale, CA $120k–$240k/yr Published 6 months ago

Python UVM Perl SystemVerilog

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Sunnyvale, CA $135k–$180k/yr Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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