← Back to results

Principal Engineer - Standard Cell Design

Location
US, California, Santa Clara
Compensation
Not disclosed
Level
principal
Type
full time

Posted by employer 2 months ago

First seen on Joblaze 1 week ago

Last verified on the company career page 1 day ago

Apply at Intel → Save job Scanned from intel.com

Not disclosed in this posting: compensation, years of experience, work arrangement, visa sponsorship.

Joblaze summary

In this role, the Principal Engineer focuses on the design and development of standard cell libraries, ensuring they meet performance and power specifications. Proficiency in digital design, semiconductor physics, and tools like Cadence or Synopsys is essential for success. This position is ideal for experienced engineers with a strong background in VLSI design and a track record of leading complex projects. Intel's emphasis on innovation and cutting-edge technology makes this a dynamic environment for those looking to make a significant impact.

Joblaze insights

Quick facts

What seniority level is this role?
Intel targets principal-level candidates for this position.
Is this full-time or contract?
Full-time for this Principal Engineer - Standard Cell Design role at Intel.

Similar positions

Intel
Senior Standard Cell Library Engineer
Intel · US, California, Santa Clara
Intel
Senior Design Verification Engineer
Intel · US, California, Santa Clara
Intel
Director, SoC Design Engineering
Intel · US, California, Santa Clara
Intel
Director, Silicon Design Engineering
Intel · US, California, Santa Clara
Intel
Principal Collateral Device Engineer
Intel · US, California, Santa Clara