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Process Engineer, Wafer Preparation & Assembly (Starlink/Akoustis)

Join SpaceX as a Process Engineer to develop and optimize wafer preparation processes for cutting-edge RF filters.

Location
Bastrop, TX
Compensation
Not disclosed
Level
mid
Type
full time · On-site

Posted by employer 5 days ago

First seen on Joblaze 3 days ago

Last verified on the company career page 1 day ago

What you'll build

  • Develop and qualify wafer back-grinding processes
  • Optimize mechanical wafer dicing
  • Establish post-dice die cleaning methods
  • Develop laser marking processes for wafers
  • Run DOEs and troubleshoot defects

Must have

  • Bachelor's degree in chemical engineering, materials science, or mechanical engineering
  • 2+ years of hands-on experience in semiconductor wafer processing

Nice to have

  • 3+ years of hands-on semiconductor manufacturing experience
  • Experience with SiC or other hard materials
  • Laser marking of wafers or die
  • Familiarity with DOE, SPC, Cp/Cpk, FMEA, or Six Sigma
  • CAD familiarity (AutoCAD or SolidWorks)

Practical constraints

  • Onsite in Bastrop, TX
  • Up to 20% domestic and international travel
  • Willingness to work extended hours or weekends

Requirements

Experience
2–3 years
Education
Bachelor's degree
Visa
No sponsorship (stated in posting)

Not disclosed in this posting: compensation.

Joblaze summary

The Process Engineer for Wafer Preparation and Assembly at SpaceX focuses on developing and optimizing processes for wafer thinning, dicing, and die preparation to ensure high-quality outputs. Key skills include hands-on experience with semiconductor manufacturing, particularly in wafer processing and mechanical dicing, along with familiarity in statistical process control and data analysis tools. This role is suited for candidates with a background in engineering and at least two years of relevant experience, ideally in a semiconductor environment. The position involves collaboration with cross-functional teams and may require travel to support manufacturing efforts.

Joblaze insights

  • Listed 3 days ago — first seen on Joblaze November 4, 2026. Last confirmed on SpaceX's careers page November 6, 2026.
  • Statistical Process Control appears in 0.6% of 3411 comparable mid other roles in United States; Semiconductor appears in 0.4% of 3411 comparable mid other roles in United States.

Quick facts

Is the Process Engineer, Wafer Preparation & Assembly (Starlink/Akoustis) role remote?
No — this is an on-site role in Bastrop, TX.
How much experience is required?
2–3 years of relevant experience for this Process Engineer, Wafer Preparation & Assembly (Starlink/Akoustis) role.
Where is the role based?
SpaceX is hiring for this position in Bastrop, TX.
What's the tech stack?
Joblaze extracted these technologies from the posting: Semiconductor, Statistical Process Control, dicing, die preparation, laser marking, thinning.
What seniority level is this role?
SpaceX targets mid-level candidates for this position.
Is this full-time or contract?
Full-time for this Process Engineer, Wafer Preparation & Assembly (Starlink/Akoustis) role at SpaceX.

From the original posting

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PROCESS ENGINEER, WAFER PREPARATION & ASSEMBLY (STARLINK/AKOUSTIS)

Akoustis is now operating as a wholly owned subsidiary of SpaceX providing industry leading RF filters using patented XBAW technology to help drive the mission of making human life multi-planetary, while also connecting the world through Starlink. Our work helps further the impact that Starlink is already making on millions of users around the world, while allowing us to broaden that reach dramatically and continue connecting the unconnected here on earth.

We are looking for a hands-on Process Engineer to develop, optimize, qualify, and implement the full wafer-to-die preparation flow: wafer thinning and backside processing, dicing, die cleaning and handling, laser marking, inspection, and final package singulation. You will work directly with equipment and cross-functional partners (package engineering, assembly, test, reliability, quality, and external manufacturers) to deliver high-quality die that support downstream yield and reliability.

RESPONSIBILITIES

  • Develop and qualify wafer back-grinding, thinning, stress-relief, and backside finishing processes; set thickness, TTV, bow, warp, and roughness targets while minimizing chipping, cracking, subsurface damage, and edge defects
  • Develop and optimize mechanical wafer dicing (including thin wafers and difficult materials such as SiC); select blades, tapes, and parameters (speed, feed, depth, coolant, dressing, single- or multi-pass) and control chipping, sidewall quality, delamination, and street/exclusion requirements
  • Establish post-dice die cleaning, drying, handling, tape mount/release (UV and non-UV), pick, sort, and presentation methods that protect die integrity, orientation, and traceability for flip-chip, wire-bond, and other assembly flows
  • Develop and qualify laser marking processes for wafers and bare die (including green/UV sources); optimize mark contrast and resolution while avoiding damage to electrical performance, metallization, passivation, or mechanical integrity, and implement vision/OCR verification
  • Develop final package singulation (saw, laser, or mechanical) for organic, mold, ceramic, and metal structures; minimize cracking, chipping, delamination, burrs, and edge defects and confirm impact on warpage, electrical performance, and reliability
  • Run DOEs, define process windows and controls, troubleshoot defects, qualify equipment and consumables, incorporate supplier and production feedback, and transfer robust processes into manufacturing

BASIC QUALIFICATIONS

  • Bachelor's degree in chemical engineering, materials science, mechanical engineering, or other engineering discipline
  • 2+ years of hands-on experience in semiconductor wafer processing, thinning, dicing, die preparation, or manufacturing (Internship or extracurricular experience is applicable)

PREFERRED SKILLS AND EXPERIENCE

  • 3+ years of hands-on semiconductor manufacturing experience, including wafer back-grinding/thinning (including ≤150 µm wafers) and mechanical dicing/blade selection
  • Experienced in operating and developing processes on semiconductor equipment, plus solid understanding of wafer and die handling, process troubleshooting, and statistical process control
  • Experience with SiC or other hard materials, dicing tapes, blade dressing, two-step or partial-depth cutting, thin-film wafers, and die pick/handling equipment
  • Laser marking of wafers or die (green, UV, or similar) and machine-vision/OCR mark verification.
  • Package singulation and understanding of warpage, stress, cracking, chipping, and delamination mechanisms
  • DOE, SPC, Cp/Cpk, FMEA, or Six Sigma; data analysis with JMP, Minitab, MATLAB, or Python.
  • Equipment qualification, process transfer, OSAT/external partner support, and familiarity with JEDEC, SEMI, or IPC standards
  • CAD familiarity (AutoCAD or SolidWorks) is a plus

ADDITIONAL REQUIREMENTS

  • Onsite in Bastrop, TX (not remote or hybrid)
  • Up to 20% domestic and international travel for supplier and manufacturing support
  • Willingness to work extended hours or weekends to support key milestones
  • Ability to work in a semiconductor manufacturing environment, follow safety and cleanroom requirements, and perform light physical tasks (including lifting up to 25 lbs and handling wafers, substrates, packages, and tooling)
  • Strong written and verbal communication skills with engineering, manufacturing, suppliers, and management

ITAR REQUIREMENTS:

Standard company text repeated across SpaceX's postings is omitted here.