Joblaze summary

In the role of Senior Microarchitecture Researcher at IonQ, the individual will focus on the physical implementation and design of fault-tolerant architectures for ion trap quantum processors. Key skills include expertise in quantum error correction, classical chip architecture, and simulation techniques, with a strong background in quantum computing or related fields. This position is well-suited for someone with several years of research experience who can effectively collaborate across diverse scientific disciplines. IonQ's team emphasizes a collaborative approach to advancing quantum computing technology.

Joblaze insights

Listed today — first seen on Joblaze November 6, 2026. Last confirmed on IonQ's careers page November 6, 2026.
Salary band is above the typical range for comparable tech roles (median ~$127,600).
Starts above 87% of 1287 comparable senior other roles in United States we track (median $143,000 across 186 companies).
Simulation Tools appears in 0.1% of 2657 comparable senior other roles in United States; quantum computing appears in 0.1% of 2657 comparable senior other roles in United States.

Quick facts

What's the salary range?: IonQ lists $188,000–$282,000 for this role.
How much experience is required?: At least 4 years of relevant experience for this Senior Microarchitecture Researcher role.
What's the tech stack?: Joblaze extracted these technologies from the posting: Simulation Tools, chip architecture, quantum computing, quantum error correction.
What seniority level is this role?: IonQ targets senior candidates for this position.
Is this full-time or contract?: Full-time for this Senior Microarchitecture Researcher role at IonQ.

From the original posting

About IonQ:

Role Overview

Role:

We are looking for a Microarchitecture (uArch) Researcher. As a uArch researcher, you will be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world's best quantum computers to solve the world's most complex problems.

In this role, you will contribute to the physical implementation, design and layout of fault-tolerant architectures in ion trap quantum processors. You will work on implementing, tailoring, simulating and designing large-scale chip architectures that support fault-tolerant quantum computation. Your work will directly contribute to the physical and logical architecture of the quantum chips of the future.

Responsibilities:

You will take quantum error correction protocols from theory to a physical layout on ion trap processors, and build the simulation tools that tell us how those layouts perform under realistic noise.

The work is deeply collaborative. You will work alongside trap designers, AMO physicists, QEC researchers and colleagues from a broad range of research backgrounds, and share your results through papers and other technical writing.

Key responsibilities include:

Contribute to the physical implementation of quantum error correction protocols on ion trap processors.
Contribute to a library of simulation tools that analyse logical performance under realistic physical noise models.
Collaborate with trap designers, AMO physicists, QEC researchers and a broad spectrum of other research backgrounds.
Contribute to research papers and other technical writing.

Requirements:

To succeed, you will need four years of research experience in either quantum computing or chip architecture, and a degree in quantum computing, physics, engineering, chemistry or a related field.

You will bring strong expertise in one or more of AMO theory, QEC theory, QCVV theory or classical VLSI theory, and be comfortable applying it to the architecture of real quantum hardware.

You’d be a great fit with:

Strong expertise with quantum simulation techniques, including at the physical, gate, circuit and QEC level.
Experience with classical chip architecture and an interest in quantum chip architecture.
Experience with quantum error correction, logical operations and decoders.
The ability to communicate at every level, from the research community to the business to PhD level.

The total compensation package includes base salary, bonus, equity, and a range of benefits available on our career site.

If this role has a commission structure, the compensation range below just reflects the base compensation range.

Wage Transparency:

$188,000—$282,000 USD

Compensation will vary based on individual factors such as education, qualifications, and experience of the final candidate(s), specific office location, and calibration against relevant market data and internal team equity. Posted base salary figures are subject to change as new market data becomes available. Our benefits include comprehensive medical, dental, and vision plans, matching 401(k), unlimited PTO and paid holidays, parental/adoption leave, legal insurance, and a home technology stipend. Details of participation in these benefit plans will be provided when a candidate receives an offer of employment.

Standard company text repeated across IonQ's postings is omitted here.

Senior Microarchitecture Researcher