Senior Principal Engineer-DFT
Posted by employer 2 days ago
First seen on Joblaze 2 hours ago
Last verified on the company career page 2 hours ago
Not disclosed in this posting: compensation, years of experience, visa sponsorship.
Joblaze summary
In this role, the Senior Principal Engineer for Design for Test (DFT) at Marvell Semiconductor focuses on developing and implementing test strategies to ensure product reliability and performance. The position requires expertise in DFT methodologies, as well as proficiency in tools and languages such as Verilog and SystemVerilog. This role is ideal for seasoned engineers with a strong background in semiconductor design and testing, looking to leverage their skills in a collaborative environment. Marvell Semiconductor is known for its innovative approach in the semiconductor industry, making this a pivotal role within the team.
Joblaze insights
- Listed today — first seen on Joblaze November 6, 2026. Last confirmed on Marvell Semiconductor's careers page November 6, 2026.
Quick facts
- Is the Senior Principal Engineer-DFT role remote?
- No — this is an on-site role in Santa Clara, CA, United States.
- Where is the role based?
- Marvell Semiconductor is hiring for this position in Santa Clara, CA, United States.
- What seniority level is this role?
- Marvell Semiconductor targets principal-level candidates for this position.
- Is this full-time or contract?
- Full-time for this Senior Principal Engineer-DFT role at Marvell Semiconductor.