Senior Principal Engineer, RTL ASIC Design
Posted by employer 4 months ago
First seen on Joblaze 5 days ago
Last verified on the company career page 1 day ago
Not disclosed in this posting: compensation, years of experience, work arrangement, visa sponsorship.
Joblaze summary
In this role, the Senior Principal Engineer focuses on designing and implementing RTL for ASIC projects, ensuring high performance and efficiency. Proficiency in Verilog, SystemVerilog, and familiarity with ASIC design flows are essential for success. This position is ideal for experienced engineers with a strong background in digital design and a track record of leading complex projects. Marvell Semiconductor is known for its innovative approach in the semiconductor industry, making this a dynamic environment for technical growth.
Joblaze insights
- Listed 5 days ago on Joblaze — tracked directly from Marvell Semiconductor's career page.
- Marvell Semiconductor has 164 other open roles including Digital IC Design Engineer, Intern, Hardware Validation (Test Solutions) Engineer, AI Infrastructure Engineer Intern.
Quick facts
- What seniority level is this role?
- Marvell Semiconductor targets principal-level candidates for this position.
- Is this full-time or contract?
- Full-time for this Senior Principal Engineer, RTL ASIC Design role at Marvell Semiconductor.