Drive the two-qubit gate performance of superconducting quantum processors in a role with substantial autonomy and ownership.
Posted by employer 1 month ago
First seen on Joblaze 1 week ago
Last verified on the company career page 1 day ago
Not disclosed in this posting: compensation, years of experience, work arrangement, visa sponsorship.
Joblaze summary
In this role, the Senior Quantum Engineer focuses on enhancing the performance of two-qubit gates in superconducting quantum processors through experimental design and execution. Key skills include pulse engineering, calibration methodologies, and error suppression strategies, all aimed at identifying and mitigating sources of gate errors. This position is ideal for experienced professionals with a strong background in quantum engineering and a collaborative mindset, as it involves significant autonomy and cross-disciplinary teamwork. The role is critical to advancing Rigetti Computing's roadmap toward effective error correction in quantum computing.
Quick facts
- What's the tech stack?
- Joblaze extracted these technologies from the posting: error suppression, pulse engineering, quantum computing, superconducting quantum processors.
- What seniority level is this role?
- Rigetti Computing targets senior candidates for this position.
- Is this full-time or contract?
- Full-time for this Senior Quantum Engineer, Gate Calibration role at Rigetti Computing.
From the original posting
We are looking for an experienced Quantum Engineer to drive the two-qubit gate performance of our tunable-coupler superconducting quantum processors.
Two-qubit gate fidelity is one of the most consequential challenges in quantum computing, and it sits at the center of our roadmap toward error correction. In this role, you will design, execute, and interpret the experiments that propel our near- and long-term gate performance at scale. You will identify the dominant sources of two-qubit gate error on our processors, isolate their physical origin, and eliminate them — through pulse engineering, calibration methodology, error suppression strategies, or feedback to design and fabrication. Your conclusions will directly inform device design, control strategy, and platform-level decisions.
This is a role with substantial autonomy and ownership. You will directly influence the technical direction for gate performance work through the rigorous design and execution of your test plans, measurement and improvement of relevant metrics and error budgeting, and shaping of research priorities. You will do this in a deeply collaborative environment spanning device design, fabrication, control systems, software, theory and R&D, turning proofs of concept into robust procedures that hold up across hundreds of qubit pairs.