"pcie protocol analysers" Jobs

7 open tech roles matching “pcie protocol analysers”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: Python, C++, SystemVerilog. Every listing is re-checked daily and closed roles are removed.

Showing 7 of 7 results

Senior ASIC Emulation Engineer

Join K2 Space as a Senior ASIC Emulation Engineer to lead the deployment and optimization of pre-silicon emulation platforms.

K2 Space United States - Remote $170k–$250k/yr Published 1 month ago

C++ palladium ZeBu Python Veloce

Flexible on stack

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Senior ASIC Emulation Engineer

Lead the bring-up, deployment, and optimization of pre-silicon emulation platforms in a high-growth satellite company.

K2 Space Seattle, WA $170k–$250k/yr Published 1 month ago

palladium ZeBu Python Veloce Perl

Flexible on stack

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Senior Firmware Validation Engineer

Join Graphcore as a Senior Firmware Validation Engineer to validate firmware for ARM-based server platforms in AI deployments.

Graphcore Austin, Texas, United States Published 1 week ago

OpenBMC ARM CI/CD UEFI EDK II

Flexible on stack

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Senior Debug Validation Engineer

Lead post-silicon debug and validation activities for next-generation AI compute silicon and systems at Graphcore.

Graphcore Bengaluru, India Published 2 months ago

PCIe C++ Lauterbach JTAG JLink

Flexible on stack

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Senior FPGA Engineer (TS/SCI)

Join K2 Space as a Senior FPGA Engineer to develop and verify FPGA firmware for cutting-edge spacecraft.

K2 Space Los Angeles, CA $120k–$225k/yr Published 1 month ago

C++ Rust Python SystemVerilog VHDL

Flexible on stack

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Senior FPGA Engineer

Join K2 Space as a Senior FPGA Engineer to develop and verify FPGA firmware for cutting-edge spacecraft.

K2 Space Los Angeles, CA $120k–$225k/yr Published 5 months ago

C++ Rust Python SystemVerilog VHDL

Flexible on stack

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Senior FPGA Engineer

Join K2 Space as a Senior FPGA Engineer to develop and verify FPGA firmware for cutting-edge spacecraft.

K2 Space Seattle, WA $120k–$225k/yr Published 2 months ago

C++ Rust Python SystemVerilog VHDL

Flexible on stack

Apply →