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Systemverilog Jobs

16 open positions · Updated 4 days ago

Average salary: 150.9k–215.3k/yr

Showing 16 of 16 positions

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FPGA Verification Engineer, Air Dominance and Strike

PCIe MIL-STD-1553 JESD204C Vivado Makefile

Costa Mesa, CA, USA

$123k–$193k/yr

Indexed 4 days ago Apply →

Design Verification Engineer- Tile Remote

Cerebras Systems

Python UVM Perl SystemVerilog

Sunnyvale, CA

$120k–$240k/yr

Published 4 months ago Apply →

Design Verification Engineer (Silicon Engineering) Visa

Python UVM SystemVerilog MATLAB

Sunnyvale, CA

$135k–$185k/yr

Published 3 months ago Apply →

Design Verification Engineer (Silicon Engineering) Visa

Python UVM SystemVerilog MATLAB

Irvine, CA

$125k–$175k/yr

Published 3 months ago Apply →

Design Verification Engineer (Silicon Engineering) Visa

Python UVM SystemVerilog MATLAB

Redmond, WA

$125k–$175k/yr

Published 3 months ago Apply →

SOC Design Verification Engineer (Silicon Engineering) Visa

Python UVM SystemVerilog MATLAB

Irvine, CA

$125k–$175k/yr

Published 3 months ago Apply →

SOC Design Verification Engineer (Silicon Engineering) Visa

computer science Computer Engineering ASIC Electrical Engineering Python

Sunnyvale, CA

$135k–$185k/yr

Published 1 month ago Apply →

RTL Design Engineer (Silicon Engineering) Visa

APB Verilog AHB DSP Python

Irvine, CA

$125k–$175k/yr

Published 1 month ago Apply →

Senior FPGA Engineer, EW

PCIe RF Verilog JESD Git

Costa Mesa, CA, USA

$191k–$253k/yr

Indexed 4 days ago Apply →

Principal ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Hawthorne, CA

$200k–$285k/yr

Published 2 weeks ago Apply →

Principal ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Palo Alto, CA

$210k–$295k/yr

Published 1 week ago Apply →

Sr. ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Palo Alto, CA

$170k–$235k/yr

Published 1 week ago Apply →

Sr. ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Hawthorne, CA

$160k–$225k/yr

Published 2 weeks ago Apply →

Senior FPGA Engineer

PCIe RF RFSoC Git Xilinx

Costa Mesa, CA, USA

$191k–$253k/yr

Indexed 4 days ago Apply →

Sr. FPGA Engineer (Starshield) Visa

C++ Verilog DSP FPGA SystemVerilog

Hawthorne, CA

$160k–$225k/yr

Published 2 months ago Apply →

FPGA Engineer (Starshield) Visa

TCP C++ Ethernet 802.3 Verilog Xilinx SoC FPGA

USA

$120k–$170k/yr

Published 2 months ago Apply →

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