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SystemVerilog Jobs

78 open positions · Updated 9 hours ago

Average salary (USD/year): 148.3k–232.3k/yr

78 roles Senior 24, Mid 23, Intern 10, Principal 9, Staff 9, Director 3 1–20 yrs experience Austin +25 more Full-time, Internship newest 9 hours ago

Also hiring: Python Verilog C++ UVM TCL C

78 SystemVerilog roles across 14 companies, most in Other; 1% fully remote; typical advertised salary $135k

Who is hiring (14 companies)

K2 Space (14) SpaceX (14) Etched (13) Graphcore (10) Ambiq (6)

Role types

Other (67) AI/ML (9) Design (2)

Work arrangement: 1 fully remote · 8 hybrid · 15 on-site · 54 not stated

Advertised salaries: p25 $125k · median $135k · p75 $170k (from 35 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 78 positions

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Director, Logical Design

Lead the design and development of complex SoCs for next-generation AI acceleration platforms at Graphcore.

Graphcore Bengaluru, India Published 1 day ago

Verilog Digital Design ASIC SystemVerilog Microarchitecture

Flexible on stack

Sr. FPGA Design Engineer

Join Reliable Robotics as a Sr. FPGA Design Engineer to enhance aviation safety through innovative technology.

Reliable Robotics Corporation Mountain View, CA Published 4 days ago

Verilog SystemVerilog VHDL

FPGA Engineer (Starshield)

Design and develop FPGAs for SpaceX's satellite constellation, focusing on safety-critical logic and communications systems.

SpaceX Hawthorne, CA $125k–$195k/yr Published 1 week ago

C++ Verilog C Xilinx SoC FPGA Python

Flexible on stack

DFT Engineer

Join Ricursive Intelligence as a DFT Engineer to shape the future of chip design with AI-driven methodologies.

Ricursive Intelligence Palo Alto Published 1 week ago

IJTAG Verilog DFT Python TCL

Flexible on stack

Sr. RF Silicon Software Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RF Silicon Software Engineer to develop low-level software for Starlink's advanced communication systems.

SpaceX Redmond, WA $165k–$270k/yr Published 3 weeks ago

C++ C FPGA Python SystemVerilog

Flexible on stack

RF Silicon Software Engineer (RFIC Engineering) Visa

Join SpaceX as an RF Silicon Software Engineer to develop low-level software for Starlink's RF silicon.

SpaceX Redmond, WA $125k–$200k/yr Published 3 weeks ago

C++ C FPGA Python SystemVerilog

Flexible on stack

DFT Intern

Join Ambiq as a DFT Intern to gain hands-on experience in low power DFT implementation and verification for ultra-low power chips.

Ambiq Singapore Published 3 weeks ago

Verilog Shell Python TCL SystemVerilog

Staff FPGA Engineer Hybrid

Join IonQ as a Staff FPGA Engineer to design and develop FPGA features for advanced quantum systems.

IonQ Oxford, England, United Kingdom Published 2 months ago

Verilog USB UART JTAG Vivado

Flexible on stack

Staff Analog Mixed-Signal Design and Modelling Engineer Hybrid

Join IonQ as a Senior Staff Analog Mixed-Signal Design and Modelling Engineer to shape the future of quantum computing.

IonQ Oxford, England, United Kingdom Published 2 months ago

Verilog-A Verilog-AMS Python Cadence AMS Designer SystemVerilog

Flexible on stack

Senior FPGA Verification Engineer Hybrid

Join IonQ as a Senior FPGA Verification Engineer to shape advanced quantum control systems with a collaborative team.

IonQ Oxford, England, United Kingdom Published 2 months ago

Python UVM SystemVerilog

Flexible on stack

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 3 weeks ago

C++ Xilinx Vivado Verilog C DSP

Flexible on stack

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 3 weeks ago

C++ Xilinx Vivado Verilog C DSP

Flexible on stack

FPGA Associate (Winter 2027)

Join Astranis as an FPGA Associate to work on hardware development for advanced satellite technology.

Astranis San Francisco $1.9k–$1.9k/wk Published 1 month ago

Verilog Vivado IDE Xilinx FPGA TCL

Flexible on stack

FPGA Intern (Summer 2027) Visa

Join Astranis as an FPGA Intern to work on hardware development for advanced satellite technology.

Astranis San Francisco $29–$29/hr Published 1 month ago

Verilog Vivado IDE Xilinx FPGA UVM

Flexible on stack

FPGA Intern (Winter 2027)

Join Astranis as an FPGA Intern to work on hardware development for advanced satellite technology.

Astranis San Francisco $29–$29/hr Published 1 month ago

Verilog Xilinx Vivado FPGA UVM

Flexible on stack

FPGA Associate (Summer 2027)

Join Astranis as an FPGA Associate to work on hardware development for advanced satellite systems.

Astranis San Francisco $1.9k–$1.9k/wk Published 1 month ago

Verilog Xilinx Vivado FPGA UVM

Flexible on stack

Silicon Validation Engineer, Software

Join Etched as a Silicon Validation Engineer to develop firmware for AI/ML accelerator ASICs in a hands-on, onsite role.

Etched San Jose Published 1 month ago

C++ Verilog C CI/CD JTAG

Flexible on stack

Design Verification Engineer - Interface IP

Join Etched as a Design Verification Engineer to tackle complex verification challenges in a fast-paced startup environment.

Etched San Jose Published 1 year ago

PCIe ARC ARM UVM SystemVerilog

Flexible on stack

Design Verification Engineer - Internal IP Hybrid

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched Austin Published 6 months ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

Design Verification Engineer - SoC Hybrid

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched Austin Published 6 months ago

Python SystemVerilog

Flexible on stack

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