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Systemverilog Jobs

16 open positions · Updated 1 month ago

Average salary: 153k–219.3k/yr

Showing 16 of 16 positions

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Design Verification Engineer Remote

Cerebras Systems Sunnyvale, CA $120k–$240k/yr Published 6 months ago

Python UVM Perl SystemVerilog

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Sunnyvale, CA $135k–$180k/yr Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$175k/yr Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $125k–$175k/yr Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 2 months ago

APB Verilog AHB DSP Python

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Palo Alto, CA $210k–$295k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $160k–$225k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Palo Alto, CA $170k–$235k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 1 week ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Lead ASIC Design Verification Engineer (Starshield Satellite Engineering) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 1 month ago

Python UVM SystemVerilog

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Sr. FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 3 months ago

C++ Verilog DSP FPGA SystemVerilog

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FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $120k–$170k/yr Published 3 months ago

TCP C++ Ethernet 802.3 Verilog Xilinx SoC FPGA

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