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Cadence Jaspergold Jobs

1 open positions · Updated 3 days ago

1 role Senior 1 5 yrs experience San Jose Full-time newest 3 days ago

Also hiring: Siemens Questa Formal Synopsys VC Formal SystemVerilog SystemVerilog Assertions

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Formal Verification - DV

Join Etched as a Formal Verification Engineer to drive verification strategies for complex ASIC designs in a fast-paced startup environment.

Etched San Jose Published 3 months ago

SystemVerilog Assertions Synopsys VC Formal Siemens Questa Formal SystemVerilog Cadence JasperGold

Flexible on stack

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