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Cadence Tempus Jobs

2 open positions · Updated 21 hours ago

2 roles Senior 2 5–10 yrs experience San Jose, South San Francisco, California, United States Full-time newest 21 hours ago
Also hiring: Cadence Innovus Synopsys Fusion Compiler Synopsys PrimeTime 3DIC Ansys RedHawk-SC Cadence Genus

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Neuralink
Physical Design and Verification Engineer

Join Neuralink as a Senior Physical Design Engineer to lead advanced-node, multi-die 3DIC product implementations.

Neuralink South San Francisco, California, United States $131k–$265k/yr Published 1 day ago
Synopsys PrimeTime Synopsys ICC2 Cadence Voltus 3DIC RTL
Flexible on stack
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Etched
Physical Design Engineer - Full Chip Implementation

Own full-chip implementation for frontier inference clusters at a cutting-edge AI hardware startup.

Etched San Jose Published 3 months ago
Synopsys PrimeTime Calibre Synopsys Fusion Compiler Cadence Tempus Pegasus
Flexible on stack
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