Own full-chip implementation for frontier inference clusters at a cutting-edge AI hardware startup.
Posted by employer 2 months ago
First seen on Joblaze 13 hours ago
Last verified on the company career page 13 hours ago
Skills & Technologies
What you'll build
- Own full-chip clocking across all PVT corners and modes
- Manage MMMC timing closure at the top level
- Drive functional and timing ECO closure
- Own end-to-end physical verification closure
- Debug complex PV violations
Must have
- 10+ years of previous experience with chip planning
- Experience with top-level and full-chip closure on advanced process nodes
- Experience with Cadence or Synopsys automated RTL-to-GDSII flows
- Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
- Experience with Pegasus or Calibre for physical verification signoff
Nice to have
- Familiarity with modern ML and LLM model architectures
- Ability to program with Python or another scripting language
- Familiarity with AI tools for programming/coding
- Startup experience or comfort working in fast-paced environments
Requirements
- Experience
- 10+ years
Not disclosed in this posting: compensation, visa sponsorship.
Benefits
Joblaze summary
In this role, the Physical Design Engineer will manage full-chip implementation tasks, including floorplanning, timing analysis, and physical verification, ensuring timely delivery of high-performance AI hardware. Proficiency in tools like Cadence Innovus and Synopsys PrimeTime is essential, along with extensive experience in chip planning and advanced process nodes. This position is suited for seasoned engineers with a strong background in physical design and a creative approach to problem-solving. Etched fosters a collaborative environment where engineering and research intersect, emphasizing rapid iteration and innovation.
Joblaze insights
- Listed today — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page September 21, 2026.
Quick facts
- Is the Physical Design Engineer - Full Chip Implementation role remote?
- No — this is an on-site role in San Jose, United States.
- How much experience is required?
- At least 10 years of relevant experience for this Physical Design Engineer - Full Chip Implementation role.
- Where is the role based?
- Etched is hiring for this position in San Jose, United States.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: Cadence Innovus, Cadence Tempus, Calibre, Pegasus, Synopsys Fusion Compiler, Synopsys PrimeTime.
- What seniority level is this role?
- Etched targets senior candidates for this position.
- Is this full-time or contract?
- Full-time for this Physical Design Engineer - Full Chip Implementation role at Etched.
From the original posting
Job Summary
Etched is building a new category of AI hardware: frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation—encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs—from synthesis through to GDSII completion. You will lead critical efforts in these areas, leveraging our PD flows to drive aggressive PPA optimization and timing closure. You will collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.
Key Responsibilities
Own full-chip clocking across all PVT corners and modes.
Manage MMMC (Multi-Mode Multi-Corner) timing closure at the top level.
Own timing constraints and hierarchical timing budgeting between top level and blocks.
Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.
Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.
You may be a good fit if you have
10+ years of previous experience with chip planning, top level PD, floorplanning
Experience with top-level and full-chip closure on advanced process nodes (5nm and below)
Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
Experience with Pegasus or Calibre for physical verification signoff
Experience with hierarchical timing budgeting, constraint management, and ECO closure
Experience with Cadence Innovus for top-level assembly, routing, and layout fixes
Deeply creative and able to think from first principles
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
Ability to program with Python or another scripting language
Familiarity with AI tools for programming/coding
Startup experience or comfort working in fast-paced environments
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2.5k per month for those living within walking distance of the office
Daily lunch and dinner in our office
Unlimited compute budget subject to ROI justification
Standard company text repeated across Etched's postings is omitted here.