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Fpgas Jobs

56 open positions · Updated 1 month ago

Average salary: 169.2k–235.6k/yr

Showing 20 of 56 positions

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FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $120k–$170k/yr Published 4 months ago

TCP C++ Ethernet 802.3 Verilog Xilinx SoC FPGA

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 2 weeks ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 2 months ago

APB Verilog AHB DSP Python

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Sr. FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 4 months ago

C++ Verilog DSP FPGA SystemVerilog

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Sr. ASIC Design Engineer (Starshield)

SpaceX Irvine, CA $160k–$225k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield)

SpaceX Palo Alto, CA $210k–$295k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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New Graduate Engineer, ASIC Design (Starshield) Visa

Join SpaceX as a New Graduate Engineer in ASIC Design, working on advanced technologies for national security and space applications.

SpaceX USA $125k–$150k/yr Published 1 day ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Flexible on stack

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LLM Inference Performance & Evals Engineer

Cerebras Systems Toronto, Ontario, Canada Published 10 months ago

C++ Triton LLVM AI/ML linear-attention

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Staff Kernel Optimzation Engineer

Cerebras Systems Remote, California, United States Published 4 months ago

C++ PyTorch TensorFlow Python

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Sr. ASIC Design Engineer (Starshield)

SpaceX Palo Alto, CA $170k–$235k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Palo Alto, CA $210k–$295k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $160k–$225k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Palo Alto, CA $170k–$235k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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