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Verilog

20 jobs tagged Verilog

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Sunnyvale, CA $170k–$235k/yr Published 1 week ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 1 week ago

C++ Verilog Siemens Tessent ATE RTL

Flexible on stack

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 1 week ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $200k–$285k/yr Published 1 week ago

C++ Verilog Siemens Tessent RTL DFT

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 1 week ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 1 week ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. ASIC Design Engineer (Starshield)

SpaceX Irvine, CA $160k–$225k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 4 weeks ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $120k–$170k/yr Published 3 months ago

TCP C++ Ethernet 802.3 Verilog Xilinx SoC FPGA

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RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 2 months ago

APB Verilog AHB DSP Python

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Principal DFT Engineer (Silicon Engineering) Visa

SpaceX Sunnyvale, CA $210k–$295k/yr Published 3 months ago

C++ Verilog Siemens Tessent UPF RTL

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. ASIC Design Engineer (Starshield)

SpaceX Palo Alto, CA $170k–$235k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield)

SpaceX Palo Alto, CA $210k–$295k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 3 months ago

C++ Verilog DSP FPGA SystemVerilog

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Sr. RTL Design Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 2 months ago

Verilog AHB ASIC Python System Verilog

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Senior/Staff Engineer : Post Silicon- Bring Up Remote

Cerebras Systems Bengaluru, Karnataka, India; Sunnyvale, CA; Toronto, Ontario, Canada $175k–$275k/yr Published 3 months ago

C++ Verilog CI/CD Git AI/ML

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Senior/Staff- Engineer: Post Silicon- Bring Up Remote

Cerebras Systems Bengaluru, Karnataka, India; Sunnyvale, CA; Toronto, Ontario, Canada $175k–$275k/yr Published 3 months ago

C++ Verilog CI/CD Git Python

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