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Ipv6 Jobs in London

11968 open positions · Updated 3 months ago

Average salary: 144.1k–203.1k/yr

Showing 20 of 11968 positions

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Software Engineer (Starlink) Remote Visa

SpaceX Redmond, WA $125k–$175k/yr Published 3 months ago

C++ IPv6 DHCP OSPF BGP

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Sr. 3GPP RAN Standardization Engineer (Starlink Mobile) Visa

Join SpaceX as a Sr. 3GPP RAN Standardization Engineer to influence 5G and 6G standards and align internal engineering with global developments.

SpaceX Palo Alto, CA $170k–$230k/yr Published 1 week ago

5G physical layer design 6G network architecture ASN.1

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Wireless Systems Engineer (Starlink Mobile) Visa

SpaceX Sunnyvale, CA $135k–$185k/yr Published 2 months ago

C++ 3GPP Python MATLAB

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Sr. ASIC DFT Engineer (Silicon) Visa

Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Irvine, CA $125k–$175k/yr Published 2 months ago

C++ automated test equipment ASICs Siemens Tessent DFT

Flexible on stack

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Sr. ASIC DFT Engineer (Silicon) Visa

Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enabling global connectivity.

SpaceX Austin, TX Published 2 months ago

C++ automated test equipment ASICs Siemens Tessent DFT

Flexible on stack

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Sr. ASIC DFT Engineer (Silicon) Visa

Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Sunnyvale, CA $135k–$185k/yr Published 2 months ago

C++ automated test equipment ASICs Siemens Tessent DFT

Flexible on stack

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Irvine, CA $145k–$175k/yr Published 3 months ago

FinFET RTL Makefile ASIC Python

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Austin, TX Published 2 months ago

FinFET EDA RTL Makefile ASIC

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Palo Alto, CA $155k–$185k/yr Published 2 months ago

FinFET EDA Makefile ASIC Python

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 2 weeks ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 2 weeks ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 2 weeks ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 2 weeks ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Infrastructure Engineer Visa

Join SpaceX as an Infrastructure Engineer to design and implement global antenna sites for the Starlink satellite network.

SpaceX Redmond, WA $105k–$150k/yr Published 1 month ago

C++ Tableau PowerBI SQL Python

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

SpaceX Sunnyvale, CA $210k–$295k/yr Published 5 months ago

C++ Verilog Siemens Tessent UPF RTL

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Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 2 months ago

C++ Verilog Siemens Tessent ATE RTL

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $200k–$285k/yr Published 2 months ago

C++ Verilog Siemens Tessent RTL DFT

Flexible on stack

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 2 months ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Network Software Integration Engineer (Starlink) Visa

Join SpaceX as a Network Software Integration Engineer to enhance the Starlink network with innovative testing solutions.

SpaceX Redmond, WA $125k–$175k/yr Published 1 month ago

C++ Python Kubernetes Docker Linux

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 2 weeks ago

ASIC VMM Python UVM OVM

Flexible on stack

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