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Senior Eda Tools Jobs

13 open positions · Updated 3 weeks ago

Average salary: 156.8k–219.5k/yr

Showing 13 of 13 positions

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Sr. ASIC Design Engineer (Starshield)

SpaceX Irvine, CA $160k–$225k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. ASIC Design Engineer (Starshield)

SpaceX Palo Alto, CA $170k–$235k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX USA $170k–$230k/yr Published 1 day ago

FinFET bash ASIC Python Perl

Flexible on stack

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX USA $160k–$220k/yr Published 1 day ago

FinFET bash ASIC Python Perl

Flexible on stack

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX USA Published 1 day ago

FinFET Scripting ASIC EDA tools physical design

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Sunnyvale, CA $170k–$235k/yr Published 6 days ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 6 days ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 6 days ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 2 months ago

Verilog AHB ASIC Python System Verilog

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Sr. RFIC Layout Designer (RFIC Engineering) Visa

SpaceX Irvine, CA $135k–$195k/yr Published 3 months ago

Analog EDA RFIC Python Perl

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Sr. RFIC Layout Designer (RFIC Engineering) Visa

SpaceX Sunnyvale, CA $145k–$205k/yr Published 2 months ago

RF Analog shell scripting EDA IC layout

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Sr. RFIC Layout Designer (RFIC Engineering) Visa

SpaceX Redmond, WA $135k–$195k/yr Published 3 months ago

Analog EDA RFIC Python Perl

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