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ASIC Jobs

81 open positions · Updated 21 hours ago

Average salary (USD/year): 192.7k–291.9k/yr

81 roles Senior 38, Mid 16, Principal 14, Lead 7, Director 2, Intern 2, Junior 1, Staff 1 1–18 yrs experience Aliso Viejo, CA +21 more Full-time, Internship newest 21 hours ago

Also hiring: Python FPGA SoC CMOS DFT Perl

81 ASIC roles across 12 companies, most in Other; 2% fully remote; typical advertised salary $175k

Who is hiring (12 companies)

SpaceX (48) Etched (11) K2 Space (8) Anthropic (4) Graphcore (3)

Role types

Other (61) AI/ML (13) Management (3) Security (2) Design (1)

Work arrangement: 2 fully remote · 4 hybrid · 18 on-site · 57 not stated

Advertised salaries: p25 $165k · median $175k · p75 $200k (from 47 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 81 positions

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Sr. SOC Physical Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC Physical Verification Engineer to develop cutting-edge silicon for Starlink's global connectivity.

SpaceX Palo Alto, CA, United States $175k–$280k/yr Published 1 day ago

IC Validator Calibre ASIC Pegasus

Flexible on stack

Director, Logical Design

Lead the design and development of complex SoCs for next-generation AI acceleration platforms at Graphcore.

Graphcore Bengaluru, India Published 1 day ago

Verilog Digital Design ASIC SystemVerilog Microarchitecture

Flexible on stack

Sr. IC Package Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. IC Package Design Engineer to develop cutting-edge ASICs for space and ground infrastructures.

SpaceX Irvine, CA $165k–$265k/yr Published 4 days ago

SIWave BGA ADS HFSS RFIC

Flexible on stack

Sr. IC Package Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. IC Package Design Engineer to develop cutting-edge ASICs for space and ground infrastructures.

SpaceX Austin, TX Published 4 days ago

SIWave BGA ADS HFSS RFIC

Principal ASIC Design Engineer - Chip Lead

Join Jariet Technologies as a Principal ASIC Design Engineer to lead high-speed mixed signal/DSP projects.

CesiumAstro Aliso Viejo, CA Published 3 weeks ago

RTL design DSP high-speed mixed signal ASIC Digital Communications

Research Engineer, Chip Design RL Hybrid Visa

Join Anthropic as a Research Engineer to advance AI models' silicon design capabilities within a collaborative team.

Anthropic San Francisco, CA $500k–$850k/yr Published 6 days ago

EDA RTL FPGA reinforcement learning ASIC

Flexible on stack

Graduate Silicon Engineer 2027

Join Graphcore as a Graduate Silicon Engineer and gain hands-on experience in silicon design over a two-year program.

Graphcore Bristol, UK; Cambridge, UK Published 1 week ago

C++ C EDA ASIC Python

Flexible on stack

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 weeks ago

Verilog ASIC Python System Verilog SoC

Director - Post-Silicon Validation (Functional)

Lead a team in post-silicon validation of cutting-edge AI chips and platforms at Graphcore's new AI Engineering Campus in Austin.

Graphcore Austin, Texas, United States Published 2 weeks ago

C++ C FPGA ASIC Python

Flexible on stack

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$270k/yr Published 3 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for space and ground infrastructures.

SpaceX Irvine, CA $165k–$265k/yr Published 3 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for space and ground infrastructures.

SpaceX Austin, TX Published 3 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Distinguished PQC Cryptography & Architecture Leader

Lead the technical direction of IonQ's post-quantum cryptography hardware acceleration program in Geneva.

IonQ Geneva, Switzerland Published 1 month ago

PQC Cryptography FPGA ASIC security

Silicon Validation Engineer, Software

Join Etched as a Silicon Validation Engineer to develop firmware for AI/ML accelerator ASICs in a hands-on, onsite role.

Etched San Jose Published 1 month ago

C++ Verilog C CI/CD JTAG

Flexible on stack

Product Quality Engineer

Ensure robust quality systems for advanced AI hardware builds as a Product Quality Engineer at Etched in San Jose.

Etched San Jose Published 5 months ago

SMT PCB SPC AOI 8D

Flexible on stack

Power Integrity Engineer

Join Etched as a Power Integrity Engineer to ensure robust power delivery for high-performance ASICs in a cutting-edge hardware environment.

Etched San Jose Published 2 months ago

Power integrity VRM thermal analysis ASIC Electrical Engineering

Flexible on stack

Advanced Packaging SI/PI Engineer

Join Etched as a Senior Signal & Power Integrity Engineer to optimize electrical performance for cutting-edge AI accelerator platforms.

Etched San Jose Published 2 months ago

Power integrity Cadence Sigrity Signal integrity High Speed Interfaces ASIC

Flexible on stack

PD Intern

Join Etched as a Physical Design intern to work on front-end designs in silicon and improve iteration speed to final signoff.

Etched San Jose Published 5 months ago

ASIC Python UVM SystemVerilog SoC

Flexible on stack

Firmware Engineer

Own the accelerator software for cutting-edge chips at a frontier AI startup in San Jose.

Etched San Jose Published 5 months ago

PCIe DRAM DMA Firmware UART

Flexible on stack

DV Intern

Join Etched as a Design Verification intern to validate custom IPs for cutting-edge AI hardware in a collaborative environment.

Etched San Jose Published 8 months ago

ASIC Python UVM SystemVerilog SoC

Flexible on stack

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