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Xilinx Vivado Jobs in Irvine

1 open positions · Updated 2 days ago

1 role Mid 1 1 yrs experience Irvine, CA Full-time newest 2 days ago

Also hiring: Altera Quartus II bash C++ digital communication DSP EDA tools

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 3 days ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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