Eda Tools Jobs

8 open positions · Updated 5 hours ago

Average salary (USD/year): 140k–190k/yr

8 roles Mid 5, Senior 2, Staff 1 1–5 yrs experience Austin, TX +7 more Full-time newest 5 hours ago

Also hiring: Python ASIC CMOS FinFET TCL Perl

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Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Physical Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Austin, TX, United States Published 18 hours ago

FinFET bash ASIC Python Perl

Flexible on stack

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Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Physical Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA, United States $125k–$195k/yr Published 18 hours ago

FinFET Makefile ASIC Python Perl

Flexible on stack

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Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Physical Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Palo Alto, CA, United States $135k–$175k/yr Published 18 hours ago

FinFET bash ASIC Python Perl

Flexible on stack

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Staff Silicon Physical Design Engineer - Bengaluru

Join Graphcore as a Staff Silicon Physical Design Engineer in Bengaluru, contributing to the development of next-gen AI superchips.

Graphcore Bengaluru, India Published 1 week ago

Floorplanning Physical Verification 7nm Timing Analysis Python

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Austin, TX Published 3 months ago

FinFET Scripting ASIC EDA tools physical design

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Palo Alto, CA $170k–$230k/yr Published 3 months ago

FinFET bash ASIC Python Perl

Flexible on stack

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 3 months ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Irvine, CA $145k–$175k/yr Published 5 months ago

FinFET RTL Makefile ASIC Python

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