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Xilinx Vivado Jobs in Palo Alto

1 open positions · Updated 4 days ago

1 role Mid 1 1 yrs experience Palo Alto, CA Full-time newest 4 days ago

Also hiring: Altera Quartus II bash C++ digital communication DSP EDA tools

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ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink broadband internet system.

SpaceX Palo Alto, CA $135k–$175k/yr Published 5 days ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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