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Xilinx Vivado Jobs in Redmond

1 open positions · Updated 1 month ago

Average salary: 125k–175k/yr

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 1 month ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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