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Digital IC Design Engineer

Join Neuralink as a Digital IC Design Engineer to innovate in brain-computer interface technology with a talented team.

Location
Austin, Texas, United States; South San Francisco, California, United States
Compensation
$116k–$233.8k/yr
Level
senior
Type
full time

Posted by employer 3 years ago

First seen on Joblaze 1 month ago

Last verified on the company career page 14 hours ago

Apply at Neuralink → Save job Scanned from neuralink.com

Requirements

Experience
5+ years
Education
Bachelor's degree

Not disclosed in this posting: work arrangement, visa sponsorship.

Benefits

401k Match Equity/Stock Options Flexible Time Off Health Insurance Parental Leave

Joblaze summary

The Digital IC Design Engineer at Neuralink focuses on the micro-architecture and RTL implementation of low-power digital signal processors and hardware accelerators for advanced brain-computer interfaces. Proficiency in SystemVerilog, C/C++, and Python is essential, along with a strong background in digital design and complex systems. This role is suited for experienced engineers with at least five years in the field, particularly those with a passion for innovative technology and its applications in neuroscience. Neuralink's team is dedicated to pushing the boundaries of brain-machine interface technology.

Joblaze insights

  • Listed about a month ago — first seen on Joblaze September 3, 2026. Last confirmed on Neuralink's careers page October 27, 2026.
  • Salary band is below the typical range for comparable tech roles (median ~$129,582).
  • Starts above 8% of 290 comparable senior other roles in United States that list Python we track (median $150,000 across 55 companies). See Python salary trends
  • Python appears in 16.7% of 2570 comparable senior other roles in United States; Digital Signal Processing appears in 0.3% of 2570 comparable senior other roles in United States.

Quick facts

What's the salary range?
Neuralink lists $116,000–$233,800 for this role.
How much experience is required?
At least 5 years of relevant experience for this Digital IC Design Engineer role.
What's the tech stack?
Joblaze extracted these technologies from the posting: C, C++, Digital Signal Processing, Microarchitecture, Python, RTL.
What seniority level is this role?
Neuralink targets senior candidates for this position.
Is this full-time or contract?
Full-time for this Digital IC Design Engineer role at Neuralink.

From the original posting

About Neuralink:

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description & Responsibilities:

Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.

  • Micro-architecture design and RTL implementation of:
    • Low-power digital signal processors
    • Low-power general-purpose hardware accelerators
    • Low-power graphics processing units
    • Low-power radio MAC/PHY
    • Low-power serial link MAC/PHY
  • Design and optimization of hardware/software interface with firmware engineers
  • Application-specific architecture optimization including:
    • Complex system modeling for energy and performance benchmarks
    • Workload analysis and modeling
    • Energy/performance profiling and analysis
    • Leveraging architecture-level design trade-offs with process technology and workload type
    • Balancing cost and performance under manufacturing process variation
  • Collaboration on silicon bring-up tests with verification engineers

Required Qualifications:

  • Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
  • Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
  • 5+ years of experience in digital design
  • Expertise in SystemVerilog, C/C++, Python
  • Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
  • Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications:

  • Experience in architecture optimization with process technology customization
  • Experience in the verification of complex digital systems, using industry standard tools
  • Experience in the physical design of complex digital systems, using industry standard tools
  • Experience testing and debugging digital system-on-a-chips
  • Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
  • Experience automating tool flows
  • Experience with embedded design
  • Experience in processor instruction set architecture design
  • Experience in compiler back-end design and customization

Expected Compensation:

Base Salary Range:
$116,000—$233,800 USD

What We Offer:

Standard company text repeated across Neuralink's postings is omitted here.

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