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Rtl Jobs

50 open positions · Updated 1 month ago

Average salary: 155.3k–222.8k/yr

Showing 20 of 50 positions

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Sr. RTL Design Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 2 months ago

Verilog AHB ASIC Python System Verilog

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 1 week ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 1 week ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Sunnyvale, CA $170k–$235k/yr Published 1 week ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 2 months ago

APB Verilog AHB DSP Python

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Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 1 week ago

C++ Verilog Siemens Tessent ATE RTL

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

SpaceX Sunnyvale, CA $210k–$295k/yr Published 3 months ago

C++ Verilog Siemens Tessent UPF RTL

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $200k–$285k/yr Published 1 week ago

C++ Verilog Siemens Tessent RTL DFT

Flexible on stack

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DSP Engineer, Satellites (Starlink) Remote Visa

SpaceX Redmond, WA $125k–$175k/yr Published 2 months ago

STM32 PCM/FM BPSK Xilinx QAM

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Lead RTL Design Engineer Remote

Cerebras Systems Sunnyvale, CA $175k–$275k/yr Published 6 months ago

PCIe RDMA RTL ASIC Python

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3D Physical Design Engineer

Cerebras Systems Sunnyvale, CA $150k–$270k/yr Published 1 year ago

AI/ML Calibre ICV Python TCL

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $125k–$175k/yr Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$175k/yr Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Sunnyvale, CA $135k–$180k/yr Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$230k/yr Published 1 week ago

VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$230k/yr Published 1 week ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 week ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Sunnyvale, CA $170k–$240k/yr Published 1 week ago

ASIC VMM Python UVM OVM

Flexible on stack

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 1 week ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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