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FPGA Verification Engineer II

Join CesiumAstro as an FPGA Verification Engineer II to develop cutting-edge hardware for aerospace systems in a dynamic startup environment.

Location
Westminster, CO, United States
Compensation
Not disclosed
Level
mid
Type
full time

Posted by employer 1 day ago

First seen on Joblaze 1 day ago

Last verified on the company career page 1 day ago

Apply at CesiumAstro → Save job Scanned from cesiumastro.com

What you'll build

  • contribute to the development of FPGA circuits and systems
  • perform testing, validation, and verification of FPGA designs

Must have

  • experience in FPGA design
  • experience in verification, test, and deployment at the HDL level

Nice to have

  • experience in digital signal processing
  • experience in board-level hardware design

Practical constraints

  • must be a U.S. citizen or lawful permanent resident

Requirements

Visa
No sponsorship (stated in posting)

Not disclosed in this posting: compensation, years of experience, work arrangement.

Joblaze summary

In this role, the FPGA Verification Engineer II at CesiumAstro will focus on developing and validating FPGA circuits and systems throughout the entire development lifecycle. Key skills include expertise in FPGA design and verification at the HDL level, particularly with high-speed serial interfaces and digital processing cores. This position is suited for individuals with a solid background in hardware development, ideally in a startup environment, who thrive in collaborative and hands-on settings. The company fosters a dynamic atmosphere that encourages cross-functional engagement and innovation.

Joblaze insights

  • Listed yesterday — first seen on Joblaze November 14, 2026. Last confirmed on CesiumAstro's careers page November 14, 2026.
  • This exact title is also open at 3 other locations at CesiumAstro: Westminster, CO, Austin, TX, El Segundo, CA.
  • FPGA appears in 0.5% of 3380 comparable mid other roles in United States; Digital Signal Processing appears in 0.2% of 3380 comparable mid other roles in United States.

Quick facts

What's the tech stack?
Joblaze extracted these technologies from the posting: Digital Signal Processing, FPGA.
What seniority level is this role?
CesiumAstro targets mid-level candidates for this position.
Is this full-time or contract?
Full-time for this FPGA Verification Engineer II role at CesiumAstro.

From the original posting

Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State. At CesiumAstro, we are developers and pioneers of out-of-the-box communication systems for satellites, UAVs, launch vehicles, and other space and airborne platforms. We take pride in our dynamic and cross-functional work environment, which allows us to learn, develop, and engage across our organization. If you are looking for hands-on, interactive, and autonomous work, CesiumAstro is the place for you. We are actively seeking passionate, collaborative, energetic, and forward-thinking individuals to join our team. We are looking to add an FPGA Engineer II to our team. If you enjoy working in a startup environment, and are passionate about developing leading-edge hardware for satellites, spacecraft, and aerospace systems, we would like to hear from you.   In this position, you will contribute to the development of FPGA circuits and systems through all phases of the development process. The ideal candidate will have experience in FPGA design, verification, test, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clocks and clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Experience in digital signal processing or board-level hardware design is also desirable.

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