Member of Technical Staff, AMD GPU Kernel Engineering

About the Role

We're looking for an AMD GPU kernel engineer to make vLLM a first-class inference engine across the AMD accelerator ecosystem. A large part of this role is designing, writing, and optimizing kernels for AMD GPUs in HIP, Triton, CK, and AITER, for attention, GEMM, sampling, KV cache, and communication-heavy operations.

You'll work at the boundary of kernels, compilers, inference systems, and hardware architecture. You'll profile production-relevant models on AMD GPUs, find the bottleneck, and write the kernel that removes it, with clear correctness, latency, and throughput benchmarks. Your work will help make AMD GPU support in vLLM usable, fast, benchmarked, and maintainable.

Inferact has three kernel roles. If your kernel work is mostly on Google TPUs (Pallas, JAX), apply to TPU Kernel Engineering. If it is mostly on AMD GPUs (HIP, CK, AITER), apply to AMD GPU Kernel Engineering. For NVIDIA GPUs and cross-platform kernel work, apply to Kernel Engineering. Apply to one; we route you to the best fit.

Skills and Qualifications

Minimum qualifications:

• Bachelor's degree or equivalent experience in computer science, engineering, systems, machine learning, or similar.

• Hands-on experience designing and implementing GPU kernels in HIP, Triton, CUDA, CK, or a similar kernel language.

• Hands-on experience optimizing AMD GPU workloads using ROCm, HIP, Triton, CK, AITER, or similar AMD ecosystem tools.

• Deep understanding of AMD GPU execution, memory behavior, toolchains, kernel performance, and backend-specific performance constraints.

• Experience optimizing ML kernels such as attention, GEMM, sampling, KV cache, fused kernels, or communication-heavy kernels.

• Strong performance profiling and benchmarking skills, with the ability to use measurements, hardware counters, correctness tests, and reproducible benchmarks to guide optimization work.

Preferred qualifications:

• Experience with vLLM, SGLang, TensorRT-LLM, ROCm-based serving, or other LLM inference systems.

• Familiarity with batching, KV cache, decoding, serving tradeoffs, and backend performance constraints in production inference systems.

• Experience with compiler and kernel technologies such as Triton, MLIR, LLVM, CK, AITER, HIP, or other kernel DSLs and backend libraries.

• Knowledge of quantization methods such as INT8, FP8, mixed precision, or AMD hardware-specific numeric formats, including accuracy and performance tradeoffs.

• Experience building quantitative models of system performance, such as roofline analysis, simulation, or hardware microbenchmarking, and using them to guide kernel work.

Bonus points if you have:

• Contributed to vLLM, ROCm, HIP, Triton, CK, AITER, PyTorch, compiler projects, or other open-source ML infrastructure.

• Built AMD GPU benchmarking infrastructure or automated performance regression detection for accelerator workloads.

• Worked directly with AMD, accelerator platform teams, or early-access programs to ship backend, compiler, or inference performance improvements.

Representative projects

• Write a HIP, CK, or Triton attention or MoE kernel that beats the current default on MI300-class GPUs.

• Implement low-latency, high-throughput sampling for large language models on AMD GPUs.

• Adapt existing models for low-precision (FP8, MXFP4) inference on AMD GPUs.

• Debug kernel performance with rocprof and at the ISA level.

Logistics

• Location: This role is based in San Francisco, California. Will consider remote in the US for exceptional candidates.

• Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $400,000 USD + equity.

• Benefits: Inferact offers generous health, dental, and vision benefits as well as 401(k) company match.