Join Inferact as a TPU performance engineer to optimize vLLM for Google TPUs, enhancing AI inference performance.
Posted by employer 2 months ago
First seen on Joblaze 1 week ago
Last verified on the company career page 12 hours ago
Requirements
- Education
- Bachelor's degree
- Visa
- Sponsorship available
Not disclosed in this posting: years of experience.
Benefits
Joblaze summary
In this role, the TPU performance engineer focuses on enhancing the vLLM inference engine's performance on Google TPUs by developing and optimizing backends, compiler integrations, and benchmarking tools. Key skills include hands-on experience with JAX, XLA, and Pallas, alongside a deep understanding of TPU execution and performance constraints for machine learning workloads. This position is ideal for individuals with a strong background in computer science or engineering, particularly those experienced in optimizing ML kernels and inference paths. Inferact, founded by the creators of vLLM, operates at the cutting edge of AI inference technology.
Joblaze insights
- Listed 10 days ago on Joblaze — tracked directly from Inferact's career page.
- Inferact has 24 other open roles including IT Support & Operations Engineer, Head of Legal, Inference Engineering, Co-op.
- 116 active JAX roles on Joblaze right now.
- 109 active ML roles on Joblaze right now.
- 52 active vLLM roles on Joblaze right now.
- Salary band is in line with the typical range for AI/ML roles (median ~$188,000).
- Pays more than 48% of the 52 salaried JAX roles we track (median $200,000).
Quick facts
- Is the Member of Technical Staff, TPU Performance Engineering role remote?
- It's hybrid — Inferact expects some on-site time in San Francisco.
- What's the salary range?
- Inferact lists $200,000–$400,000 for this role.
- Where is the role based?
- Inferact is hiring for this position in San Francisco.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: JAX, ML, Pallas, TPU, XLA, vLLM.
- Does Inferact sponsor work visas for this role?
- Yes — the posting indicates visa sponsorship is available for the right candidate.
- What seniority level is this role?
- Inferact targets staff-level candidates for this position.
- Is this full-time or contract?
- Full-time for this Member of Technical Staff, TPU Performance Engineering role at Inferact.
From the original posting
Inferact's mission is to grow vLLM as the world's AI inference engine and accelerate AI progress by making inference cheaper and faster. Founded by the creators and core maintainers of vLLM, we sit at the intersection of models and hardware, a position that took years to build.
About the Role
We're looking for a TPU performance engineer to make vLLM a first-class inference engine on Google TPUs. You'll build and optimize TPU backends, compiler integrations, runtime paths, and benchmarking infrastructure using JAX, XLA, Pallas, and related tooling so vLLM can deliver frontier inference performance on TPU hardware.
You'll work at the boundary of inference systems, kernels, compilers, and hardware architecture, improving production-relevant model serving on TPU with clear correctness, latency, and throughput benchmarks. Your work will help make TPU support in vLLM usable, fast, benchmarked, and maintainable.
Skills and Qualifications
Minimum qualifications:
Bachelor's degree or equivalent experience in computer science, engineering, systems, machine learning, or similar.
Hands-on experience building or optimizing TPU workloads using JAX, XLA, Pallas, or related compiler and runtime tooling.
Deep understanding of TPU execution, memory behavior, compilation, and performance constraints for ML workloads.
Experience optimizing ML kernels or inference paths such as attention, GEMM, sampling, KV cache, fused kernels, or backend runtime paths.
Strong performance profiling and benchmarking skills, with the ability to use measurements, compiler artifacts, correctness tests, and reproducible benchmarks to guide optimization work.
Preferred qualifications:
Experience with vLLM, SGLang, TensorRT-LLM, XLA-based serving, or other LLM inference systems.
Familiarity with batching, KV cache, decoding, serving tradeoffs, and backend performance constraints in production inference systems.
Experience with compiler technologies such as XLA, MLIR, LLVM, Pallas, or other kernel DSLs, including lowering, fusion, and backend code generation.
Knowledge of quantization methods such as INT8, FP8, mixed precision, or TPU-specific numeric formats, including accuracy and performance tradeoffs.
Bonus points if you have:
Contributed to vLLM, JAX/XLA, Pallas, PyTorch/XLA, compiler projects, or other open-source ML infrastructure.
Built TPU benchmarking infrastructure or automated performance regression detection for accelerator workloads.
Worked directly with Google TPU ecosystem stakeholders, accelerator platform teams, or early-access programs to ship backend, compiler, or inference performance improvements.
Logistics
Location: This role is based in San Francisco, California. Will consider remote in the US for exceptional candidates.
Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $400,000 USD + equity.
Visa sponsorship: We sponsor visas on a case-by-case basis.
Benefits: Inferact offers generous health, dental, and vision benefits as well as 401(k) company match.