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PCB Layout Engineer (Taiwan)

Join Etched as a PCB Layout Engineer to design high-performance PCBs for cutting-edge data center products.

Location
Taipei, Taiwan
Compensation
Not disclosed
Level
senior
Type
full time · On-site

Posted by employer 1 day ago

First seen on Joblaze 1 day ago

Last verified on the company career page 1 day ago

Apply at Etched → Save job Scanned from etched.com

What you'll build

  • Design high-speed PCB layouts
  • Implement power distribution networks
  • Manage HDI PCB stack-ups
  • Collaborate with engineering teams
  • Provide input during design reviews

Must have

  • 10 years of experience in PCB layout design
  • Proficiency in Cadence Allegro PCB design tools
  • In-depth knowledge of high-speed digital design principles
  • Experience with complex HDI PCB design

Nice to have

  • Advanced degrees or certifications

Requirements

Experience
10+ years
Education
Bachelor's degree

Not disclosed in this posting: compensation, visa sponsorship.

Benefits

Equity/Stock Options Health Insurance

Joblaze summary

The PCB Layout Engineer at Etched is responsible for designing and optimizing high-speed printed circuit boards, focusing on advanced applications like 100G signaling and complex HDI stack-ups. Proficiency in Cadence Allegro and a strong background in high-speed digital design, power distribution, and thermal management are essential for this role. This position is suited for experienced engineers with a decade of relevant experience, particularly those familiar with data center hardware. Etched emphasizes a collaborative environment where engineering and research intersect, fostering innovation in AI hardware.

Joblaze insights

  • Listed yesterday — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page September 21, 2026.

Quick facts

Is the PCB Layout Engineer (Taiwan) role remote?
No — this is an on-site role in Taipei, Taiwan.
How much experience is required?
At least 10 years of relevant experience for this PCB Layout Engineer (Taiwan) role.
Where is the role based?
Etched is hiring for this position in Taipei, Taiwan.
What's the tech stack?
Joblaze extracted these technologies from the posting: Cadence Allegro, HDI PCB, PCB Design, high-speed signaling, power distribution.
What seniority level is this role?
Etched targets senior candidates for this position.
Is this full-time or contract?
Full-time for this PCB Layout Engineer (Taiwan) role at Etched.

From the original posting

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We’re seeking a skilled PCB Layout Engineer to join our dynamic team and contribute to our high-performance data center products. As a PCB Layout Engineer at Etched, you will play a crucial role in designing and optimizing printed circuit boards (PCBs) using Cadence Allegro PCB design tools. Your primary focus will be on high-speed signaling, including 100G applications, power distribution, large BGA ball-map breakouts and complex HDI PCB stack-ups for high-performance data center products. Your expertise will ensure that our products meet the highest standards of performance, reliability, and efficiency.

Key Responsibilities

  • Lead the design and optimization of high-speed PCB layouts using Cadence Allegro, tailored for 100G signaling. Implement strategies for impedance matching, trace routing, and crosstalk mitigation, resulting in robust designs that meet the stringent performance demands of modern data centers.

  • Develop and implement power distribution networks for cutting-edge data center hardware. Design power planes, decoupling strategies, and thermal management solutions to support high-performance systems, ensuring reliability and efficiency under heavy operational loads.

  • Manage the design of complex High-Density Interconnect (HDI) PCB stack-ups for multi-layer boards. Integrate blind/buried vias and microvias to meet the advanced technological requirements of data center systems, enhancing signal integrity and achieving compact form factors.

  • Collaborate with electrical and mechanical engineering teams to integrate PCB designs within the overall system architecture. Provide key input during design reviews to optimize performance, ensure manufacturability, and align with system-level objectives in a data center environment.

You maybe a good fit if you

  • Have a Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field. Advanced degrees or certifications are a plus.

  • Are equipped with 10 years of experience in PCB layout design with a focus on high-speed signaling, power distribution, and HDI stack-ups, ideally for high-performance data center products.

  • Demonstrate proficiency in Cadence Allegro PCB design tools

  • Command in-depth knowledge of high-speed digital design principles, including signal integrity and impedance control.

  • Have Experience with complex HDI PCB design and manufacturing processes.

  • Understand power distribution network design and thermal management techniques, particularly for data center applications.

  • Are excellent at problem-solving skills and attention to detail.

We encourage you to apply even if you do not believe you meet every single qualification.

Benefits

  • Competitive compensation packages, including generous equity packages

  • Comprehensive insurance coverage and other top-of-market benefits

  • US onboarding experience in our Silicon Valley HQ

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

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