Lead advanced ASIC package architecture and execution for high-performance mixed-signal and digital SoCs at K2 Space.
Posted by employer 5 days ago
First seen on Joblaze 3 days ago
Last verified on the company career page 1 day ago
What you'll build
- Own ASIC package architecture for FC-BGA and MCM solutions
- Lead package-level trade studies
- Define long-term packaging roadmap
- Establish organizational package design standards
- Drive detailed design of FC-BGA packages
Must have
- Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field
- 10+ years of experience in ASIC package design
- Deep expertise in FC-BGA
- Proven experience delivering high-pin-count, high-performance ASIC packages
- Strong understanding of substrate technologies and materials
Nice to have
- Experience with MCM or heterogeneous integration
- Background in high-speed digital or mixed-signal SoCs
- Familiarity with aerospace, space, or high-reliability electronics
- Experience defining packaging strategy from early architecture
- Demonstrated history of building or scaling package design methodology
Requirements
- Experience
- 10+ years
- Education
- Bachelor's degree
Not disclosed in this posting: work arrangement, visa sponsorship.
Benefits
Joblaze summary
The Principal ASIC Package Design Engineer at K2 Space is responsible for leading the design and execution of advanced ASIC package architectures, focusing on flip-chip BGA and multi-chip module solutions. This role requires expertise in high-performance mixed-signal and digital SoCs, with a strong emphasis on package-level trade studies and collaboration with silicon and systems teams. Ideal candidates will have over a decade of experience in ASIC package design and a solid understanding of substrate technologies and thermal management. K2 Space is positioned for rapid growth, aiming to produce a significant number of high-power satellites.
Joblaze insights
- Listed 3 days ago — first seen on Joblaze September 17, 2026. Last confirmed on K2 Space's careers page September 19, 2026.
- This exact title is also open at 1 other location at K2 Space: United States - Remote.
- Salary band is above the typical range for comparable tech roles (median ~$126,887).
- Starts above 60% of 72 comparable principal other roles in United States we track (median $190,000 across 25 companies).
- ASIC appears in 6.2% of 162 comparable principal other roles in United States; HFSS appears in 0.6% of 162 comparable principal other roles in United States.
Quick facts
- What's the salary range?
- K2 Space lists $200,000–$280,000 for this role.
- How much experience is required?
- At least 10 years of relevant experience for this Principal ASIC Package Design Engineer role.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: ADS, ASIC, FC-BGA, HFSS, MCM, SIWave.
- What seniority level is this role?
- K2 Space targets principal-level candidates for this position.
- Is this full-time or contract?
- Full-time for this Principal ASIC Package Design Engineer role at K2 Space.
From the original posting
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The Role
We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.
Responsibilities
- Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
- Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
- Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
- Establish organizational package design standards, methodologies, and best practices.
- Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
- Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
- Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
- Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
- Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
- Manage relationships with external packaging vendors, substrate suppliers, and
- OSATs, including vendor qualification, capability assessment, contract negotiation, and performance/quality score carding to ensure roadmap and volume commitments are met.
- Drive material selection, substrate technology choices, and assembly process optimization.
Required Qualifications
- Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
- 10+ years of experience in ASIC package design, with deep expertise in FC-BGA.
- Proven experience delivering high-pin-count, high-performance ASIC packages into production.
- Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
- Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
- Experience working directly with OSATs and substrate vendors.
- Knowledge of packaging qualification and test methodologies.
Preferred Qualifications
- Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
- Background in high-speed digital or mixed-signal SoCs.
- Familiarity with aerospace, space, or high-reliability electronics.
- Experience defining packaging strategy from early architecture through first silicon and volume ramp.
- Demonstrated history of building or scaling package design methodology within an organization.
Compensation and Benefits:
- Base salary range for this role is $200,000 – $280,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
Standard company text repeated across K2 Space's postings is omitted here.