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Senior ASIC Package Design Engineer

Join K2 Space as a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture for high-performance satellites.

Location
Seattle, WA
Compensation
$180k–$260k/yr
Level
senior
Type
full time

Posted by employer 6 days ago

First seen on Joblaze 4 days ago

Last verified on the company career page 18 hours ago

Apply at K2 Space → Save job Scanned from k2space.com

Skills & Technologies

What you'll build

  • Define ASIC package architecture for FC-BGA and MCM solutions
  • Lead package-level trade studies
  • Establish package design standards
  • Drive detailed design of FC-BGA packages
  • Manage relationships with external packaging vendors

Must have

  • 5+ years of experience in ASIC package design
  • Deep expertise in FC-BGA
  • Proven experience delivering high-pin-count ASIC packages
  • Strong understanding of substrate technologies and materials
  • Fluent in SI/PI and EM simulation tools

Nice to have

  • Experience with MCM or heterogeneous integration
  • Background in high-speed digital or mixed-signal SoCs
  • Familiarity with aerospace, space, or high-reliability electronics

Requirements

Experience
5+ years
Education
Bachelor's degree

Not disclosed in this posting: work arrangement, visa sponsorship.

Benefits

Equity/Stock Options Paid Time Off Health Insurance Parental Leave

Joblaze summary

The Senior ASIC Package Design Engineer at K2 Space focuses on developing advanced package architectures, particularly for flip-chip BGA and multi-chip module solutions, ensuring high-performance ASICs meet stringent design standards. Key skills include expertise in substrate technologies, signal integrity, and thermal management, with a strong emphasis on collaboration with silicon and systems teams. This role is suited for experienced engineers with a background in ASIC design and a proven track record in high-pin-count packages. K2 Space is in a high-growth phase, aiming to revolutionize satellite technology.

Joblaze insights

  • Listed 4 days ago — first seen on Joblaze September 17, 2026. Last confirmed on K2 Space's careers page September 21, 2026.
  • This exact title is also open at 1 other location at K2 Space: United States - Remote.
  • Salary band is above the typical range for comparable tech roles (median ~$126,887).
  • Starts above 88% of 17 comparable senior other roles in United States that list ASIC we track (median $165,000 across 3 companies).
  • ASIC appears in 1.3% of 2159 comparable senior other roles in United States; MCM appears in 0.1% of 2159 comparable senior other roles in United States.

Quick facts

What's the salary range?
K2 Space lists $180,000–$260,000 for this role.
How much experience is required?
At least 5 years of relevant experience for this Senior ASIC Package Design Engineer role.
What's the tech stack?
Joblaze extracted these technologies from the posting: ADS, ASIC, FC-BGA, HFSS, MCM, SIWave.
What seniority level is this role?
K2 Space targets senior candidates for this position.
Is this full-time or contract?
Full-time for this Senior ASIC Package Design Engineer role at K2 Space.

From the original posting

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The Role

We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role supports the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will collaborate with internal teams for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

Responsibilities

  • Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
  • Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
  • Establish package design standards, methodologies, and best practices.
  • Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
  • Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
  • Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
  • Support package-level SI/PI strategy, including high-speed digital interfaces, power delivery network (PDN) design, and decoupling strategy
  • Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
  • Manage relationships with external packaging vendors, substrate suppliers, and
    OSATs.
  • Drive material selection, substrate technology choices, and assembly process optimization.

Qualifications

  • Bachelor’s degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
  • 5+ years of experience in ASIC package design, with deep expertise in FC-BGA.
  • Proven experience delivering high-pin-count, high-performance ASIC packages into production.
  • Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
  • Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
  • Experience working directly with OSATs and substrate vendors.
  • Knowledge of packaging qualification and test methodologies.

Nice to Have

  • Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
  • Background in high-speed digital or mixed-signal SoCs.
  • Familiarity with aerospace, space, or high-reliability electronics.

Compensation and Benefits:

  • Base salary range for this role is $180,000 – $260,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

Standard company text repeated across K2 Space's postings is omitted here.

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