What's the salary range?

K2 Space lists $170,000–$250,000 for this role.

How much experience is required?

At least 5 years of relevant experience for this Senior Serdes Characterization & Post-Silicon Validation Engineer role.

What's the tech stack?

Joblaze extracted these technologies from the posting: BER, NRZ, PAM4, Python, RX, SERDES.

What seniority level is this role?

K2 Space targets senior candidates for this position.

Senior Serdes Characterization & Post-Silicon Validation Engineer at K2 Space

Joblaze summary

In this role, the engineer will focus on the bring-up, characterization, and validation of high-speed SerDes interfaces within complex system-on-chips (SoCs). Key skills include expertise in high-speed serial-link fundamentals, proficiency with advanced measurement equipment, and experience in developing automated testing environments. This position is ideal for someone with over five years of relevant experience, particularly in high-speed SerDes characterization and post-silicon validation. K2 Space is in a high-growth phase, aiming to scale its satellite production significantly.

Joblaze insights

Listed 7 days ago — first seen on Joblaze September 19, 2026. Last confirmed on K2 Space's careers page September 25, 2026.
This exact title is also open at 1 other location at K2 Space: Los Angeles, CA.
Salary band is above the typical range for comparable tech roles (median ~$126,887).
Starts above 72% of 238 comparable senior other roles in United States that list Python we track (median $150,000 across 53 companies). See Python salary trends
Python appears in 16.4% of 2270 comparable senior other roles in United States; PAM4 appears in 0.1% of 2270 comparable senior other roles in United States.

Quick facts

What's the salary range?: K2 Space lists $170,000–$250,000 for this role.
How much experience is required?: At least 5 years of relevant experience for this Senior Serdes Characterization & Post-Silicon Validation Engineer role.
What's the tech stack?: Joblaze extracted these technologies from the posting: BER, NRZ, PAM4, Python, RX, SERDES.
What seniority level is this role?: K2 Space targets senior candidates for this position.
Is this full-time or contract?: Full-time for this Senior Serdes Characterization & Post-Silicon Validation Engineer role at K2 Space.

From the original posting

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

About the Role
We are looking for a hands-on Senior SerDes Characterization & Post-Silicon Validation Engineer to bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs.

You will work closely with SerDes/IP, mixed-signal, digital, firmware, SI/PI, package, board, and systems teams to take high-speed interfaces from first silicon through product integration and system-level operation. You will also help build our high-speed test and validation capability from the ground up.

Responsibilities

Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces.
Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions.
Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin.
Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior.
Perform BER and stress testing across representative and worst-case channels.
Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic.
Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.
Partner with firmware and digital teams on SerDes configuration, initialization, diagnostics, adaptation, and system-level link bring-up.
Develop automated characterization and regression environments for instrument control, data collection, analysis, and reporting.
Support the transition from chip-level SerDes characterization to product integration and system-level validation.
Contribute to building the high-speed validation lab, equipment, test infrastructure, measurement methodology, and automation from the ground up.

Qualifications

BS/MS in Electrical Engineering, Computer Engineering, or related field.
5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.
Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.
Deep hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
Experience with eye diagrams, jitter decomposition, bathtub curves, BER testing, stressed-eye testing, and receiver sensitivity characterization.
Strong understanding of package/PCB channels, insertion/return loss, crosstalk, reflections, and channel de-embedding.
Experience developing automated characterization environments using Python or similar scripting languages and instrument-control interfaces.
Strong debugging skills across silicon, package, PCB, firmware, and system boundaries.
Ability to work closely with SerDes IP/design, SI, package, board, firmware, and digital teams.

Preferred Qualifications

Experience with 112G+ PAM4 SerDes characterization and validation.
Experience with Ethernet, PCIe, JESD204, Interlaken, or chip-to-chip interfaces.
Experience with compliance testing and high-speed interface standards.
Familiarity with SerDes behavioral/channel models and simulation-to-measurement correlation.
Experience with SerDes IP integration and validation from third-party IP vendors.
Experience with advanced package and high-loss PCB channels.
Familiarity with high-speed clocking, PLLs, reference-clock jitter, and power-supply noise effects on SerDes performance.
Experience with automated PVT characterization and large-scale measurement data analysis.

Compensation and Benefits:

Base salary range for this role is $170,000 – $250,000 + equity in the company
Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

Standard company text repeated across K2 Space's postings is omitted here.

Senior Serdes Characterization & Post-Silicon Validation Engineer

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