"synopsys vc formal" Jobs

2 open tech roles matching “synopsys vc formal”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: SystemVerilog, SystemVerilog Assertions, Verilog. Every listing is re-checked daily and closed roles are removed.

Showing 2 of 2 results

Formal Verification - DV

Join Etched as a Formal Verification Engineer to drive verification strategies for complex ASIC designs in a fast-paced startup environment.

Etched San Jose Published 3 months ago

SystemVerilog Assertions Synopsys VC Formal Siemens Questa Formal SystemVerilog Cadence JasperGold

Flexible on stack

Apply →

Applications Engineer Hybrid

Join ChipAgents as an Applications Engineer to guide enterprise customers in deploying AI-driven chip design solutions.

ChipAgents San Jose $130k–$350k/yr Published 3 months ago

lint Verilog CDC shell scripting Python

Flexible on stack

Apply →