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Hdl Simulators Jobs

3 open positions · Updated 1 day ago

Average salary (USD/year): 128.3k–190k/yr
3 roles Mid 3 1 yrs experience Irvine, CA +2 more Full-time newest 1 day ago
Also hiring: Altera Quartus II bash C++ digital communication DSP EDA tools

Showing 3 of 3 positions

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SpaceX
ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink broadband internet system.

SpaceX Palo Alto, CA, United States $135k–$175k/yr Published 2 days ago
C++ Xilinx Vivado Verilog DSP HDL simulators
Flexible on stack
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SpaceX
FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 1 week ago
C++ Xilinx Vivado Verilog DSP HDL simulators
Flexible on stack
Apply →
SpaceX
FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 1 week ago
C++ Xilinx Vivado Verilog DSP HDL simulators
Flexible on stack
Apply →

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