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Lead Verilog Jobs

1 open positions · Updated 3 hours ago

Average salary: 190k–245k/yr

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Manager, ASIC Design Engineering (Starshield Satellite Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

USA

$190k–$245k/yr

Published 9 hours ago Apply →

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