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Questa Jobs

11 open positions · Updated 3 days ago

Average salary: 179.4k–253.9k/yr

Showing 11 of 11 positions

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sunnyvale, CA

$170k–$235k/yr

Published 3 months ago Apply →

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Quartus II Xilinx Vivado Verilog AHB IES

Redmond, WA

$160k–$225k/yr

Published 3 months ago Apply →

Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Irvine, CA

$200k–$285k/yr

Published 3 months ago Apply →

Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Redmond, WA

$200k–$285k/yr

Published 3 months ago Apply →

Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sunnyvale, CA

$210k–$295k/yr

Published 3 months ago Apply →

Sr. ASIC Design Engineer (Starshield)

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Hawthorne, CA

$160k–$225k/yr

Published 2 weeks ago Apply →

Sr. ASIC Design Engineer (Starshield)

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Palo Alto, CA

$170k–$235k/yr

Published 1 week ago Apply →

FPGA Verification Engineer, Air Dominance and Strike

PCIe MIL-STD-1553 JESD204C Vivado Makefile

Costa Mesa, CA, USA

$123k–$193k/yr

Indexed 3 days ago Apply →

Principal ASIC Design Engineer (Starshield) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Hawthorne, CA

$200k–$285k/yr

Published 2 weeks ago Apply →

Principal ASIC Design Engineer (Starshield)

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Palo Alto, CA

$210k–$295k/yr

Published 1 week ago Apply →

Sr. RTL Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sunnyvale, CA

$170k–$235k/yr

Published 1 month ago Apply →

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