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RTL design Jobs

3 open positions · Updated 6 days ago

3 roles Mid 1, Principal 1 3–10 yrs experience Aliso Viejo, CA +2 more Full-time newest 6 days ago

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CesiumAstro

Join Jariet Technologies as a Principal ASIC Design Engineer to lead high-speed mixed signal/DSP projects.

CesiumAstro Aliso Viejo, CA Published 4 weeks ago
ChipAgents

Own the technical success of top-tier semiconductor accounts and drive AI adoption in chip design workflows.

ChipAgents San Jose $150k–$350k/yr Published 3 months ago
Ricursive Intelligence

Explore opportunities at Ricursive Intelligence, a frontier AI Lab focused on self-improving systems and chip design.

Ricursive Intelligence Palo Alto Published 3 months ago