"systemverilog" Jobs

65 open tech roles matching “systemverilog”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: SystemVerilog, Python, UVM. Every listing is re-checked daily and closed roles are removed.

Showing 20 of 65 results

Formal Verification - DV

Join Etched as a Formal Verification Engineer to drive verification strategies for complex ASIC designs in a fast-paced startup environment.

Etched San Jose Published 4 months ago

SystemVerilog Assertions Synopsys VC Formal Siemens Questa Formal SystemVerilog Cadence JasperGold

Flexible on stack

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Design Verification Engineer - Internal IP

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched San Jose Published 1 year ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

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Design Verification Engineer - Internal IP Hybrid

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched Austin Published 6 months ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

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Design Verification Engineer - Interface IP

Join Etched as a Design Verification Engineer to tackle complex verification challenges in a fast-paced startup environment.

Etched San Jose Published 1 year ago

PCIe ARC ARM UVM SystemVerilog

Flexible on stack

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Design Verification Engineer - Interface IP Hybrid

Join Etched as a Design Verification Engineer to tackle complex verification challenges in a fast-paced startup environment.

Etched Austin Published 6 months ago

PCIe ARC ARM UVM SystemVerilog

Flexible on stack

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Design Verification Engineer - SoC

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched San Jose Published 1 year ago

Python SystemVerilog

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Digital Verification Engineer

Join Neuralink as a Digital Verification Engineer to impact the future of brain-computer interfaces.

Neuralink South San Francisco, California, United States $131k–$243k/yr Published 3 months ago

ARM Unix Makefile Python UVM

Flexible on stack

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Design Verification Engineer - SoC Hybrid

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched Austin Published 6 months ago

Python SystemVerilog

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DV Intern

Join Etched as a Design Verification intern to validate custom IPs for cutting-edge AI hardware in a collaborative environment.

Etched San Jose Published 8 months ago

ASIC Python UVM SystemVerilog SoC

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Staff Engineer - Design Verification

Join Ambiq as a Staff Engineer to verify digital and mixed-signal designs for low-power semiconductor solutions.

Ambiq Singapore Published 4 months ago

C++ Verilog ARM C Makefile

Flexible on stack

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Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 2 months ago

APB Verilog ARM AHB C/C++

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Sr. Staff Engineer - Digital Design Verification Visa

Join Ambiq as a Sr. Staff Engineer to lead digital design verification for cutting-edge low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 4 months ago

APB Verilog ARM AHB C/C++

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 3 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 3 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 3 months ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Silicon Verification Engineer - Multiple Levels Hybrid

Join Graphcore as a Silicon Verification Engineer to ensure the quality of AI compute hardware through effective verification processes.

Graphcore Bristol, UK; Cambridge, UK Published 4 months ago

Git Python UVM SystemVerilog SVA

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Emulation Engineer, Hardware Prototyping (HAPS)

Join Etched as an Emulation Engineer to own HAPS bring-up and support firmware and software engineers in a cutting-edge AI hardware startup.

Etched San Jose $150k–$275k/yr Published 5 months ago

C++ Protium Verilog SimVision palladium

Flexible on stack

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Analog IC Design and Verification Engineer

Join Neuralink as a senior Analog IC Design and Verification Engineer to innovate in brain-machine interface technology.

Neuralink Austin - ATX1; Austin, Texas, United States; South San Francisco, California, United States $125k–$291k/yr Published 1 year ago

Verilog-AMS SystemVerilog CMOS

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Senior FPGA Verification Engineer Hybrid

Join IonQ as a Senior FPGA Verification Engineer to shape advanced quantum control systems with a collaborative team.

IonQ Oxford, England, United Kingdom Published 2 months ago

Python UVM SystemVerilog

Flexible on stack

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