Systemverilog Jobs in South San Francisco

6 open positions · Updated 1 week ago

Average salary (USD/year): 125.6k–240.9k/yr

6 roles Mid 3, Senior 2, Intern 1 2–5 yrs experience Austin, Texas, United States; South San Francisco, California, United States, South San Francisco, California, United States Full-time, Internship newest 1 week ago

Also hiring: Python C++ AI/ML AMBA ARM CMOS

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Electrical Engineer, Compute Architecture

Join Neuralink as an Electrical Engineer to design and oversee custom electronics systems for innovative healthcare solutions.

Neuralink Austin, Texas, United States; South San Francisco, California, United States $105k–$175.5k/yr Published 3 months ago

PCIe MIPI Verilog LVDS SLVS-EC

Flexible on stack

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Analog IC Design and Verification Engineer

Join Neuralink as a senior Analog IC Design and Verification Engineer to innovate in brain-machine interface technology.

Neuralink South San Francisco, California, United States $125k–$291k/yr Published 1 year ago

Verilog-AMS SystemVerilog CMOS

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Digital IC Design Engineer

Join Neuralink as a Digital IC Design Engineer to innovate in brain-computer interface technology with a talented team.

Neuralink Austin, Texas, United States; South San Francisco, California, United States $116k–$233.8k/yr Published 3 years ago

C++ RTL Python hardware accelerators SystemVerilog

Flexible on stack

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Hardware/ Software Co-Design Engineer

Join Neuralink as a Hardware/Software Co-Design Engineer to innovate in brain-computer interface technology.

Neuralink Austin, Texas, United States; South San Francisco, California, United States $151k–$261k/yr Published 6 months ago

C++ AI/ML Rust Python SystemVerilog

Flexible on stack

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Digital Verification Engineer

Join Neuralink as a Digital Verification Engineer to impact the future of brain-computer interfaces.

Neuralink South San Francisco, California, United States $131k–$243k/yr Published 1 month ago

ARM Unix Makefile Python UVM

Flexible on stack

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Digital IC Design Engineer Intern

Join Neuralink as a Digital IC Design Engineer Intern to work on next-gen chip design for brain-computer interfaces.

Neuralink South San Francisco, California, United States $35–$35/hr Published 10 months ago

C++ Python SystemVerilog

Flexible on stack

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