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Product Engineer, Silicon Validation

Lead silicon validation and test program development for large-format AI accelerator chips at a cutting-edge startup.

Location
San Jose
Compensation
Not disclosed
Level
senior
Type
full time · On-site

Posted by employer 6 months ago

First seen on Joblaze 1 month ago

Last verified on the company career page 19 hours ago

Apply at Etched → Save job Scanned from etched.com

What you'll build

  • Plan and execute silicon characterization
  • Lead test cost optimization efforts
  • Drive yield improvement initiatives
  • Manage relationships with test vendors
  • Productize test programs for manufacturing

Must have

  • Bachelor's or Master's degree in Electrical Engineering or related field
  • 5-10+ years of hands-on experience in silicon validation
  • Proven track record in yield optimization
  • Experience with silicon characterization methodologies
  • High-volume manufacturing test experience
  • Strong understanding of test program debugging

Nice to have

  • Experience with Advantest V93K platforms
  • GPU, HPC, or AI accelerator chip testing background
  • HBM or high-speed memory interface testing experience
  • Leading NPI through high-volume production
  • Scripting and automation skills
  • Cross-functional leadership in silicon bring-up

Requirements

Experience
5–10 years
Education
Bachelor's degree

Not disclosed in this posting: compensation, visa sponsorship.

Benefits

Wellness Benefits Daily Meals Housing Subsidy Unlimited Compute Budget Health Insurance Relocation Assistance

Joblaze summary

The Product Engineer for Silicon Validation at Etched is responsible for leading the silicon validation process, developing test strategies, and ensuring high-quality production of AI accelerator chips. This role requires expertise in silicon characterization, yield optimization, and ATE test development, particularly for advanced node semiconductors. Ideal candidates will have 5-10 years of hands-on experience in product engineering and a strong background in high-volume manufacturing. Etched fosters a collaborative environment where engineering and research intersect, emphasizing cross-functional teamwork.

Joblaze insights

  • Listed about a month ago — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page November 10, 2026.
  • Python appears in 52.5% of 568 comparable senior ai/ml roles in United States; Perl appears in 0.4% of 568 comparable senior ai/ml roles in United States.

Quick facts

Is the Product Engineer, Silicon Validation role remote?
No — this is an on-site role in San Jose.
How much experience is required?
5–10 years of relevant experience for this Product Engineer, Silicon Validation role.
Where is the role based?
Etched is hiring for this position in San Jose.
What's the tech stack?
Joblaze extracted these technologies from the posting: AI/ML, ATE, Computer Engineering, Electrical Engineering, Perl, Python.
What seniority level is this role?
Etched targets senior candidates for this position.
Is this full-time or contract?
Full-time for this Product Engineer, Silicon Validation role at Etched.

From the original posting

Job Summary

We are seeking an experienced Product Engineer to lead silicon validation, test program

development, and productization for our large-format AI accelerator chips. In this role, you will develop and execute test strategies from first silicon through high-volume manufacturing, partnering with cross-functional teams and external vendors to ensure production quality and cost targets. This role is critical to achieving first-pass silicon success and seamless NPI-to-HVM transitions.

Key Responsibilities

  • Planning and executing comprehensive silicon characterization from first silicon through production release, including voltage-frequency-temperature characterization, corner testing, guard band determination, and production limit setting

  • Lead test cost optimization efforts while maintaining quality standards

  • Architect test flows to balance test time, coverage, and yield learning objectives for complex AI accelerator designs

  • Drive systematic yield improvement initiatives through data-driven root cause analysis using statistical tools and methods

  • Establish and track key quality metrics including DPPM and test escapes

  • Perform die/package level bring-ups, troubleshoot failure modes, and resolve issues by collaborating with design, system validation, and operations teams

  • Support OSAT bring-up, manage ATE/SLT manufacturing test program releases, and drive toward aggressive test cost goals

  • Productize test programs and methodologies for seamless transition from engineering to high-volume manufacturing

  • Analyze field return data and system-level failures to identify test coverage gaps and implement improved screening methods

  • Drive ATE-system correlation activities to ensure test program accuracy and validate performance against system specs

  • Manage relationships with test vendors, OSAT partners, and foundry partners

You may be a good fit if you have (Must-have qualifications)

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

  • 5-10+ years of hands-on experience in silicon validation, product engineering, and ATE test development for advanced node semiconductors

  • Proven track record in yield optimization and DPPM reduction with quantifiable results

  • Experience with silicon characterization methodologies including Fmax/Vmin characterization and power/thermal validation

  • High-volume manufacturing test experience with demonstrated production scale results

  • Proficiency in yield and fail pareto analysis using JMP, Exensio, DataPower, or OptimalPlus

  • Strong understanding of test program debugging, failure analysis correlation, and yield enhancement techniques

Strong candidates may also have experience with (Nice-to-have qualifications)

  • Experience developing and optimizing ATE test programs for wafer sort and final test on

    Advantest V93K platforms

  • Experience managing wafer sort and final test across multiple advanced process nodes

  • GPU, HPC, or AI accelerator chip testing background with production scale results

  • HBM or high-speed memory interface testing and characterization experience

  • Leading NPI through high-volume production with multi-vendor qualification across multiple OSAT sites

  • Driving significant cost reduction initiatives

  • Multi-site parallel testing strategies and test time optimization for large-format dies

  • Scripting and automation skills (Python, Perl, TCL) for test data analysis and workflow automation

  • Cross-functional leadership in silicon bring-up and manufacturing ramp

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Housing subsidy of $2.5k per month for those living within walking distance of the office

  • Daily lunch and dinner in our office

  • Unlimited compute budget subject to ROI justification

 

Standard company text repeated across Etched's postings is omitted here.