Joblaze summary

The STA/Timing Closure Lead at ChipAgents focuses on developing strategies for timing closure on complex integrated circuits, including 3D designs. This role requires extensive experience with STA and timing tools, particularly in advanced process nodes, and a strong background in electrical engineering. Ideal candidates will have over a decade of experience in timing closure at top-tier design houses and a willingness to engage directly with customers to refine product offerings. ChipAgents emphasizes collaboration with a skilled technical team and aims to innovate within the semiconductor industry.

Joblaze insights

Listed 3 days ago — first seen on Joblaze October 31, 2026. Last confirmed on ChipAgents's careers page November 2, 2026.
Salary band is above the typical range for comparable tech roles (median ~$130,000).
Starts above 75% of 20 comparable lead other roles in United States that list Python we track (median $154,000 across 11 companies). See Python salary trends
Python appears in 5.7% of 618 comparable lead other roles in United States.

Quick facts

What's the salary range?: ChipAgents lists $180,000–$350,000 for this role.
How much experience is required?: At least 10 years of relevant experience for this STA/Timing Closure Lead role.
What's the tech stack?: Joblaze extracted these technologies from the posting: Design Compiler, Fusion Compiler, Python, STA, TCL, timing closure.
What seniority level is this role?: ChipAgents targets lead candidates for this position.
Is this full-time or contract?: Full-time for this STA/Timing Closure Lead role at ChipAgents.

From the original posting

About ChipAgents

ChipAgents is revolutionizing chip design and verification with agentic-AI workflows. Founded by experts in AI and semiconductor design, we partner with top-10 semiconductor companies, hyperscale cloud providers, and cutting-edge startups. Our platform accelerates RTL development, functional verification, and simulation, unlocking new levels of productivity and design quality.

Role Overview

We’re hiring an STA/Timing ClosureLead to develop solutions for closing timing on multi-billion instance ICs and 3D ICsYou’ll work with R&D to define the product architecture and refine the solution at our customer sites.

Key Responsibilities

Design our approach to timing closure for very large designs and 3D ICs with the R&D team.
Run backend and timing flows with customers and use what you learn to improve the product.
Share customer feedback with research and product teams to help set priorities.
Act as our in house expert on STA and timing closure.

Qualifications

BS or MS in Electrical Engineering, Computer Engineering, or a related field.
10+ years running STA and timing closure at a tier 1 design houses.
Experience closing timing at advanced process nodes.
Strong hands on experience with commercial synthesis and timing tools such as Design Compiler and Fusion Compiler.
Deep knowledge of STA, Liberty formats, and device characterization.
Background in device physics at advanced nodes.
Experience with die to die or chiplet to chiplet timing closure.
Experience closing timing on 3D ICs, including TSV design and interconnect timing.
Interest in working directly with customers and shaping the product.

Nice to Haves

Experience with the broader implementation flow, including place and route.
Experience using AI coding agents such as Claude Code, Codex, or OpenCode.
Scripting experience in Python, Tcl, or Makefiles.

Why ChipAgents

Use your timing expertise to build AI tools for some of the largest chips being designed today.
Work with a strong technical team and an advisory board of EDA veterans, with a product already used by real customers.

What We Offer

$180K/yr – $350K/yr base salary + equity. Open to above-scale compensation for exceptional candidates.

Standard company text repeated across ChipAgents's postings is omitted here.

STA/Timing Closure Lead