Direct from source · No middlemen

TCL Jobs

63 open positions · Updated 1 week ago

Average salary (USD/year): 158.7k–233.6k/yr
63 roles Senior 24, Mid 14, Staff 9, Principal 7, Intern 6, Director 2, Lead 1 0–15 yrs experience Austin +17 more Full-time, Internship newest 1 week ago

63 TCL roles across 9 companies, most in Other; typical advertised salary $160k

Work arrangement: 2 hybrid · 18 on-site · 43 not stated

Advertised salaries: p25 $134k · median $160k · p75 $178.8k (from 24 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 63 positions

Search with filters →
Ricursive Intelligence

Join Ricursive Intelligence as a DFT Engineer to shape the future of chip design with AI-driven methodologies.

Ricursive Intelligence Palo Alto Published 2 weeks ago
Flexible on stack
Graphcore

Join Graphcore as a Senior SLT Test Engineer to develop and deploy System Level Test solutions for next-generation AI processors.

Graphcore Austin, Texas, United States Published 3 weeks ago
Flexible on stack
Graphcore

Join Graphcore as a Principal SLT Test Engineer to lead a team in developing System Level Test capabilities for next-gen AI processors.

Graphcore Austin, Texas, United States Published 3 weeks ago
Ambiq

Join Ambiq as a DFT Intern to gain hands-on experience in low power DFT implementation and verification for ultra-low power chips.

Ambiq Singapore Published 3 weeks ago
Astranis

Join Astranis as an FPGA Associate to work on hardware development for advanced satellite technology.

Astranis San Francisco $1.9k–$1.9k/wk Published 1 month ago
Flexible on stack
Astranis

Join Astranis as an FPGA Associate to work on hardware development for advanced satellite systems.

Astranis San Francisco $1.9k–$1.9k/wk Published 1 month ago
Flexible on stack
Astranis

Join Astranis as an FPGA Intern to work on hardware development for advanced satellite technology.

Astranis San Francisco $29–$29/hr Published 1 month ago
Flexible on stack
Astranis

Join Astranis as an FPGA Intern to work on hardware development for advanced satellite technology.

Astranis San Francisco $29–$29/hr Published 1 month ago
Flexible on stack
Etched

Lead silicon validation and test program development for large-format AI accelerator chips at a cutting-edge startup.

Etched San Jose Published 5 months ago
Flexible on stack
Etched

Join Etched as a Physical Design Engineer to lead block-level implementation for cutting-edge AI hardware.

Etched Austin Published 3 months ago
Flexible on stack
Etched

Own block-level implementation from synthesis through GDSII sign-off as a Physical Design Engineer at a cutting-edge AI hardware startup.

Etched San Jose Published 3 months ago
Flexible on stack
Etched

Join Etched as a DFT Intern to refine DFT flow automation and contribute to chip-level regression in a fast-paced environment.

Etched San Jose Published 6 months ago
Flexible on stack
Etched

Join Etched as an Emulation Engineer to own HAPS bring-up and support firmware and software engineers in a cutting-edge AI hardware startup.

Etched San Jose $150k–$275k/yr Published 4 months ago
Flexible on stack
Etched

Join Etched as a Physical Design Engineer to architect cutting-edge PD flows for AI hardware in a fast-paced startup environment.

Etched San Jose Published 3 months ago
Flexible on stack
Etched

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched Austin Published 6 months ago
Flexible on stack
Etched

Join Etched as a DFT Engineer to enhance testability and product quality in cutting-edge integrated circuits.

Etched San Jose Published 8 months ago
Flexible on stack
Etched

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched San Jose Published 1 year ago
Flexible on stack
Astranis

Join Astranis as a Senior FPGA Engineer to design and verify RTL for advanced satellite systems.

Astranis San Francisco $175k–$240k/yr Published 2 years ago
Flexible on stack
SpaceX

Join SpaceX as a Physical Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 1 month ago
Flexible on stack
SpaceX

Join SpaceX as a Physical Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago
Flexible on stack
Page 1 of 4 Next →