"cmos" Jobs

7 open tech roles matching “cmos”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: ASIC, CMOS, Python. Every listing is re-checked daily and closed roles are removed.

Showing 7 of 7 results

Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

Flexible on stack

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Palo Alto, CA $170k–$230k/yr Published 3 months ago

FinFET bash ASIC Python Perl

Flexible on stack

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Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Physical Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$175k/yr Published 3 days ago

FinFET bash ASIC Python Perl

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Irvine, CA $125k–$160k/yr Published 1 month ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 month ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Redmond, WA $125k–$165k/yr Published 1 month ago

ADS Verilog DSP HFSS RTL

Flexible on stack

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Palo Alto, CA $155k–$185k/yr Published 4 months ago

FinFET EDA Makefile ASIC Python

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