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Asic Jobs in Palo Alto

11 open positions · Updated 1 week ago

Average salary: 159.3k–237.9k/yr

Showing 11 of 11 positions

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 weeks ago

ASIC VMM Python UVM OVM

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 2 weeks ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Palo Alto, CA $155k–$185k/yr Published 2 months ago

FinFET EDA Makefile ASIC Python

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 2 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 week ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

Flexible on stack

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Sr. SI/PI Engineer - Serdes, Satellites (Starlink) Visa

Join SpaceX as a Sr. SI/PI Engineer to lead signal and power integrity efforts for advanced satellite hardware in the Starlink project.

SpaceX Palo Alto, CA Published 2 weeks ago

C++ PCB DSP FPGA ASIC

Flexible on stack

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Sr. RFIC Layout Designer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Layout Designer to work on advanced silicon projects for Starlink's global broadband internet system.

SpaceX Palo Alto, CA $150k–$245k/yr Published 1 week ago

Analog EDA RFIC Python Perl

Flexible on stack

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RFIC Layout Designer (RFIC Engineering) Visa

Join SpaceX as an RFIC Layout Designer to work on advanced silicon projects for the Starlink broadband internet system.

SpaceX Palo Alto, CA $115k–$155k/yr Published 1 week ago

Analog EDA RFIC Python Perl

Flexible on stack

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Sr. Signal and Power Integrity Engineer - SI/PI, Satellites (Starlink) Visa

Join SpaceX as a Sr. Signal and Power Integrity Engineer to drive the development of advanced satellite hardware for Starlink.

SpaceX Palo Alto, CA Published 2 weeks ago

Thermal Engineering Power integrity PCB DSP RF engineering

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Sr. Hardware Design Engineer - Electrical, Satellites Payload (Starlink) Visa

Join SpaceX as a Sr. Hardware Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA Published 2 weeks ago

C++ RF PAM4 PCB Physics

Flexible on stack

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Sr. Electrical Design Engineer, Satellites Payload (Starlink) Visa

Join SpaceX as a Sr. Electrical Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA Published 2 weeks ago

C++ RF PAM4 PCB Physics

Flexible on stack

Apply →