joblaze

Direct from source · No middlemen

Asic Jobs in Palo Alto

21 open positions · Updated 16 hours ago

Average salary (USD/year): 160.3k–231.3k/yr

21 roles Senior 10, Mid 4, Junior 3, Principal 2, Lead 1, Staff 1 1–10 yrs experience Bangalore +4 more Full-time newest 16 hours ago

Also hiring: Python CMOS FPGA C++ PCB Verilog

21 Asic roles across 2 companies, most in Other; typical advertised salary $170k

Who is hiring (2 companies)

SpaceX (20) Mythic (1)

Role types

Other (20) AI/ML (1)

Work arrangement: 4 on-site · 17 not stated

Advertised salaries: p25 $135k · median $170k · p75 $175k (from 16 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 21 positions

Search with filters →

Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Physical Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Palo Alto, CA, United States $135k–$175k/yr Published 1 day ago

FinFET bash ASIC Python Perl

Flexible on stack

Apply →

Sr Staff /Staff DFT Engineer

Lead end-to-end Design for Testability implementation for complex ASIC/SoC designs at a fast-paced AI startup.

Mythic Bangalore Published 6 months ago

IJTAG Deep Neural Networks Scan DFT ASIC

Apply →

New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Redmond, WA $125k–$165k/yr Published 4 weeks ago

ADS Verilog DSP HFSS RTL

Flexible on stack

Apply →

New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 4 weeks ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

Apply →

New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Irvine, CA $125k–$160k/yr Published 4 weeks ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

Apply →

Sr. DSP Systems Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. DSP Systems Engineer to develop cutting-edge ASICs for satellite broadband systems.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

C++ RF MIMO FPGA ASIC

Flexible on stack

Apply →

ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 month ago

Verilog UPF RTL DFT ASIC

Flexible on stack

Apply →

Electrical Design Engineer, Satellites Payload (Starlink) Visa

Join SpaceX as an Electrical Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA $115k–$185k/yr Published 1 month ago

C++ RF PAM4 PCB Physics

Flexible on stack

Apply →

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 1 month ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Apply →

Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 months ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Sr. SI/PI Engineer - Serdes, Satellites (Starlink) Visa

Join SpaceX as a Sr. SI/PI Engineer to lead signal and power integrity efforts for advanced satellite hardware in the Starlink project.

SpaceX Palo Alto, CA Published 2 months ago

C++ PCB DSP FPGA ASIC

Flexible on stack

Apply →

Sr. Signal Integrity Engineer - Serdes, Satellites (Starlink) Visa

Join SpaceX as a Sr. Signal and Power Integrity Engineer to drive the development of advanced satellite hardware for Starlink.

SpaceX Palo Alto, CA Published 2 months ago

Thermal Engineering Power integrity PCB DSP RF engineering

Apply →

Sr. Hardware Design Engineer - Electrical, Satellites Payload (Starlink) Visa

Join SpaceX as a Sr. Hardware Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA Published 2 months ago

C++ RF PAM4 PCB Physics

Flexible on stack

Apply →

Sr. Electrical Design Engineer, Satellites Payload (Starlink) Visa

Join SpaceX as a Sr. Electrical Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA Published 2 months ago

C++ RF PAM4 PCB Physics

Flexible on stack

Apply →

Sr. Technical Project Lead (Silicon Engineering) Visa

Lead complex silicon projects at SpaceX, developing next-generation ASICs for Starlink's global connectivity solutions.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 months ago

Project Management Digital ASIC Design Silicon Engineering PCB FPGA

Apply →

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Palo Alto, CA $170k–$230k/yr Published 3 months ago

FinFET bash ASIC Python Perl

Flexible on stack

Apply →

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Sr. Full Chip Physical Verification Engineer (Silicon Engineering) Visa

SpaceX Palo Alto, CA $170k–$230k/yr Published 4 months ago

IC Validator Calibre Makefile ASIC Python

Apply →

Page 1 of 2 Next →