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Principal Uvm Jobs

6 open positions · Updated 3 weeks ago

Average salary: 206.7k–295.8k/yr

Showing 6 of 6 positions

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Principal Design Verification Engineer (Silicon Engineering) Visa

RTL FPGA ASIC VMM Python

Redmond, WA

$210k–$300k/yr

Published 4 months ago Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

FPGA ASIC VMM Python UVM

Sunnyvale, CA

$210k–$310k/yr

Published 4 months ago Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

FPGA ASIC VMM Python UVM

Irvine, CA

$210k–$300k/yr

Published 4 months ago Apply →

Principal ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

USA

$200k–$285k/yr

Published 1 month ago Apply →

Principal ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Hawthorne, CA

$200k–$285k/yr

Published 1 month ago Apply →

Principal ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Palo Alto, CA

$210k–$295k/yr

Published 4 weeks ago Apply →

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