How much experience is required?

At least 10 years of relevant experience for this Principal Design Verification Engineer (Silicon Engineering) role.

What's the tech stack?

Joblaze extracted these technologies from the posting: ASIC, FPGA, OVM, Python, UVM, VMM.

Does SpaceX sponsor work visas for this role?

Yes — the posting indicates visa sponsorship is available for the right candidate.

What seniority level is this role?

SpaceX targets principal-level candidates for this position.

Principal Design Verification Engineer (Silicon Engineering) at SpaceX

Joblaze summary

The Principal Design Verification Engineer at SpaceX focuses on verifying digital ASIC and FPGA designs, ensuring they meet rigorous performance standards for the Starlink network. This role requires extensive experience in design verification, including test bench development and pre- and post-silicon validation, with a strong emphasis on methodologies like UVM. Ideal candidates are seasoned engineers with a background in electrical or computer engineering, capable of thriving in a fast-paced, innovative environment. The position offers the opportunity to work on groundbreaking technology that enhances global connectivity.

Joblaze insights

Listed about 4 months ago — first seen on Joblaze May 22, 2026. Last confirmed on SpaceX's careers page October 9, 2026.
This exact title is also open at 3 other locations at SpaceX: Redmond, WA, Palo Alto, CA, Irvine, CA.
Python appears in 21.4% of 187 comparable principal other roles in United States; OVM appears in 1.6% of 187 comparable principal other roles in United States.

Quick facts

How much experience is required?: At least 10 years of relevant experience for this Principal Design Verification Engineer (Silicon Engineering) role.
What's the tech stack?: Joblaze extracted these technologies from the posting: ASIC, FPGA, OVM, Python, UVM, VMM.
Does SpaceX sponsor work visas for this role?: Yes — the posting indicates visa sponsorship is available for the right candidate.
What seniority level is this role?: SpaceX targets principal-level candidates for this position.
Is this full-time or contract?: Full-time for this Principal Design Verification Engineer (Silicon Engineering) role at SpaceX.

From the original posting

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PRINCIPAL DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

Responsible for digital ASIC and/or FPGA verification at block and system level
Lead and execute verification test plan, development, and milestones from beginning to end
Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

Bachelor’s degree in electrical engineering, computer engineering, or computer science
10+ years of experience with design verification and test bench development
10+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

Advanced degree in electrical engineering or computer engineering
Experience with verification methodologies such as UVM/OVM/VMM
Strong object-oriented programming knowledge
Strong problem-solving and coding skills
Experience in constrained random verification
Expertise in developing test plans, implementing coverage models, and analyzing results
Experience with scripting languages, e.g. Python for automation
RTL design, chip bring-up, and post-silicon validation experience
Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

Ability to work extended hours and weekends as needed to meet critical milestones

ITAR REQUIREMENTS:

Standard company text repeated across SpaceX's postings is omitted here.

Principal Design Verification Engineer (Silicon Engineering)

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