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Principal Xilinx Vivado Jobs

6 open positions · Updated 3 weeks ago

Average salary: 203.3k–288.3k/yr

Showing 6 of 6 positions

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Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Irvine, CA

$200k–$285k/yr

Published 4 months ago Apply →

Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Redmond, WA

$200k–$285k/yr

Published 4 months ago Apply →

Principal ASIC Design Engineer (Silicon Engineering) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sunnyvale, CA

$210k–$295k/yr

Published 4 months ago Apply →

Principal ASIC Design Engineer (Starshield) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

USA

$200k–$285k/yr

Published 1 month ago Apply →

Principal ASIC Design Engineer (Starshield) Visa

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Hawthorne, CA

$200k–$285k/yr

Published 1 month ago Apply →

Principal ASIC Design Engineer (Starshield)

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Palo Alto, CA

$210k–$295k/yr

Published 4 weeks ago Apply →

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